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HV461 Datasheet(PDF) 9 Page - Supertex, Inc |
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HV461 Datasheet(HTML) 9 Page - Supertex, Inc |
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9 / 14 page  HV461 9 Block Diagram and Typical Application Figure 5: Block Diagram and Typical Application VGD FAULT VREF1 ringer output SYNC VDD RESET 3 DCREF1–3 OSC Sine Wave Synthesizer 2 freq 2 AGND DVDD reset SINEREF Differential Amplifier Error Amplifier output reference Boost Converter SYNCMODE Enable Control enable PWMSYNC SW1 SW2 SW3 SW4 sync FRING VGD clk LE VDCL VREF1 PLL 20k VREF2 Precision Reference VREF1 DGND PWM Controller PWMin enable overcurrent prideadband sec delay switch drivers current limit dutycyclelimit osc ROSC freq amp offset overrange CL- CL+ CLCOMP Sync VREF2 TSYNC VREF1 20k 20k 40k 10k 20k 10k VREF1 PGND AVDD XTAL VDD VDR DIFFAMP+ DIFFAMPO DIFFAMP- PLLFLT TDB TDLY VREF1 COMP1 COMP2 VREF1 FREQ0 FREQ1 FREQ2 AMP0 AMP1 OFF0 OFF1 ENABLE +1 10 A Undervoltage Detector undervoltage Latch Offset Mux Amplitude Mux Deglitcher CFAULT referto power stage schematic VDD VDD 2 +1 1.25V 2.50V referto power stage schematic VDD RFAULT 100 VDD to host controller VDD external ring frequency CPLL2 33µF RPLL 10k CPLL1 4.7µF PLL filter only required for external ring frequency to host controller CDLY selected for desired Fault response time RFB2 4.02M RDB 4.7 CDB 120pF RDLY 4.7 CDLY 120pF CFAULT 10µF RDCL1 100 RDCL2 33 ROSC 267k RFB3 30.1k RFB1 30.1k RFB4 4.02M CCOMP2 1nF CCOMP1 47nF RCOMP 2.7k RDC1 RDC2 RDC3 RDC4 RTSYNC 3.3k CTSYNC 100nF Y1 19.6608MHz CRESET 4.7µF CREF1 100nF CREF2 100nF CDD1 10µF LGD 330µH DGD 4148 QGD TN2504 CGD 6.8µF CSINE 47nF CDD2 100nF CDC 100nF R DC1 - RDC4 selected for the desired DC Offsets. R TSYNC and CTSYNC selected for desired ring sync lead time k Ω k Ω k Ω k Ω k Ω HV461FG |
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