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WM8940CGEFL/V Datasheet(PDF) 46 Page - Cirrus Logic

Part # WM8940CGEFL/V
Description  Mono CODEC with Speaker Driver
PDF  88 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8940CGEFL/V Datasheet(HTML) 46 Page - Cirrus Logic

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WM8940
46
Rev 4.4
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R50
Speaker mixer
control
5
AUX2SPK
0
Output of auxiliary amplifier to speaker
mixer input
0 = not selected
1 = selected
1
BYP2SPK
0
Bypass path (output of input boost
stage) to speaker mixer input
0 = not selected
1 = selected
0
DAC2SPK
0
Output of DAC to speaker mixer input
0 = not selected
1 = selected
R54
Bypass path
attenuation
control
8
SPKATTN
0
Attenuation control for bypass path
(output of input boost stage) to speaker
mixer input
0 = 0dB
1 = -10dB
Table 34 Speaker Mixer Control
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R54
Speaker
volume control
7
SPKZC
0
Speaker Volume control zero cross
enable:
1 = Change gain on zero cross only
0 = Change gain immediately
6
SPKMUTE
1
Speaker output mute enable
0=Speaker output enabled
1=Speaker output muted (VMIDOP)
5:0
SPKVOL
[5:0]
111001
(0dB)
Speaker Volume Adjust
111111 = +6dB
111110 = +5dB
… (1.0 dB steps)
111001=0dB
…
000000=-57dB
Table 35 SPKOUT Volume Control
ZERO CROSS TIMEOUT
A zero-cross timeout function is also provided so that if zero cross is enabled on the input or output
PGAs the gain will automatically update after a timeout period if a zero cross has not occurred. This is
enabled by setting SLOWCLKEN. The timeout period is either 31Hz or 47Hz.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R7
Additional
control
0
SLOWCLKEN
0
Slow clock enable. Used for both the jack
insert detect de-bounce circuit and the
zero cross timeout.
0 = slow clock disabled
1 = slow clock enabled
Table 36 Timeout Clock Enable Control



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