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WM8940CGEFL/V Datasheet(PDF) 16 Page - Cirrus Logic |
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WM8940CGEFL/V Datasheet(HTML) 16 Page - Cirrus Logic |
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16 / 88 page  WM8940 16 Rev 4.4 AUDIO INTERFACE TIMING – SLAVE MODE BCLK FRAME t BCH t BCL t BCY DACDAT ADCDAT t LRSU t DS t LRH t DH t DD Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25 oC, Slave Mode, fs=48kHz, MCLK= 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 81.38 ns BCLK pulse width high tBCH 32.55 ns BCLK pulse width low tBCL 32.55 ns FRAME set-up time to BCLK rising edge tLRSU 10 ns FRAME hold time from BCLK rising edge tLRH 10 ns DACDAT hold time from BCLK rising edge tDH 10 ns DACDAT set-up time to BCLK rising edge tDS 10 ns ADCDAT propagation delay from BCLK falling edge tDD 15 ns Note: BCLK period should always be greater than or equal to MCLK period. |
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