10.8.7

LLC_AUX disconnection

If the pure external burst-mode is enabled and the LLC_AUX pin is stuck at 0 V during the burst and the

LLC_FB pin is higher than the burst comparator threshold, after 32 burst packets, the system enters LLC_AUX

disconnection protection (latched) and it is shut down if the disconnection faults detection is enabled in NVM.

10.9

ADC

The system ADC is an 8-channel 15-MHz SAR 10-bit A/D converter.

It needs 7 cycles (470 ns) for sampling and 11 cycles (740 ns) to convert the data.

It is controlled by a SW programmable scheduler allowing flexible system signals reading:

•

Fixed time sequence conversion

•

Event driven sequence conversion

Signal

Pin

Notes

FSR

Input line voltage

VAC

Internal voltage divider

484.5 V

PFC feedback voltage

PFC_FB

Direct reading

2.5 V

LLC feedback voltage

LLC_FB

Direct reading

2.5 V

10.10

Burst-mode

10.10.1

Specific resources

Burst comparator on LLC_FB pin

The LLC BURST comparator at the LLC_FB pin is used to wake-up the system, in order to perform a burst

sequence.

The comparator is alive also during sleep and the wake-up threshold is programmable (0.75 V, 1 V, 1.25 V).

External burst-mode comparator on LLC_AUX pin

The external burst-mode comparator with the 0.9 V threshold on the LLC_AUX pin is used to enter / exit the

burst-mode using an external digital signal. The external burst-mode operation can be enabled / disabled using a

NVM bit.

30-kHz system oscillator

A 30-kHz oscillator (always on) keeps the system alive.

10.10.2

Algorithm

The system can manage the deep sleep state with very low VCC current consumption (500 µA).

The system in deep sleep

•

Monitors the AC line for X-cap discharge and brown-out condition

•

Monitors the burst comparator to detect wake condition

•

Monitors the VCC for data integrity

•

All RAM data are maintained

The device implements two different burst-mode algorithms: the LLC_FB burst or external burst. The first one is

based on just the LLC_FB pin voltage, the second one is based on the external BM comparator on the LLC_AUX

pin that can be driven sensing the output current.

The burst-mode can be programmed to depends either on the LLC_FB pin only, or LLC_AUX pin only, or both.

This third possibility is called hybrid external burst.

In case of the LLC_FB burst-mode, the device enters the sleep mode if the LLC_FB pin voltage goes below a

programmable threshold. The burst switching activity is enabled after the burst comparator is triggered.

The normal switching activity is restored if the time between two bursts is lower than

a programmable threshold. This time defines a precise power level at which the controller exits the burst-mode. In

order to have a faster response to the big load transient the system exits the burst-mode also if the LLC_FB pin

voltage is still above the burst comparator threshold after one burst packet.

STNRG011A

ADC

DS13973 - Rev 2

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