PIC16F87 datasheet(49/214 Pages) MICROCHIP

49 / 214 page

 2003 Microchip Technology Inc.

Preliminary

DS30487B-page 47

PIC16F87/88

4.7.3.2

Returning to Primary Oscillator with

a RESET

A RESET will clear SCS<1:0> back to ‘00’. The

sequence for starting the primary oscillator following a

RESET is the same for all forms of RESET, including

POR. There is no transition sequence from the

alternate system clock to the primary system clock on

a RESET condition. Instead, the device will reset the

state of the OSCCON register and default to the

primary system clock. The sequence of events that

take place after this will depend upon the value of the

FOSC bits in the Configuration register. If the external

oscillator is configured as a crystal (HS, XT, or LP), the

CPU will be held in the Q1 state until 1024 clock cycles

have transpired on the primary

clock. This is

necessary because the crystal oscillator had been

powered down until the time of the transition.

During

the

oscillator

start-up

time,

instruction

execution and/or peripheral operation is suspended.

If the primary system clock is either RC, EC, or

INTRC, the CPU will begin operating on the first Q1

cycle following the wake-up event. This means that

there is no oscillator start-up time required because

the primary clock is already stable; however, there is a

delay between the wake-up event and the following

Q2. An internal delay timer of 5-10

µs will suspend

operation after the RESET to allow the CPU to

become ready for code execution. The CPU and

peripheral clock will be held in the first Q1.

The sequence of events is as follows:

A device RESET is asserted from one of many

sources (WDT, BOR, MCLR, etc.).

The device resets and the CPU start-up timer is

enabled if in SLEEP mode. The device is held in

RESET until the CPU start-up time-out is

complete.

If the primary system clock is configured as an

external oscillator (HS, XT, LP), then the OST

will be active waiting for 1024 clocks of the pri-

mary system clock. While waiting for the OST,

the device will be held in RESET. The OST and

CPU start-up timers run in parallel.

After both the CPU start-up and OST timers

have timed out, the device will wait for one addi-

tional clock cycle and instruction execution will

begin.

FIGURE 4-10:

PRIMARY SYSTEM CLOCK AFTER RESET (HS, XT, LP)

Note:

If Two-Speed Clock Start-up mode is

enabled, the INTRC will act as the system

clock until the OST timer has timed out.

Q3 Q4 Q1 Q2

OSC1

Peripheral

SLEEP

Program

0000h

T1OSI

TOST

TOSC(2)

TT1P(1)

OSC2

OSTS

System Clock

0001h

Q1 Q2 Q3 Q4 Q1 Q2

Clock

Counter

0004h

0005h

0003h

Q1 Q2 Q3 Q4

RESET

TCPU(3)

Note 1: TT1P = 30.52

µs.

2: TOSC = 50 ns minimum.

3: TCPU = 5-10

µs (1 MHz system clock).

CPU Start-up

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