M66238FP datasheet(7/11 Pages) MITSUBISHI

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MITSUBISHI

〈DIGITAL ASSP〉

M66238FP

STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER

2. Sync clock spike removal mode upon occurrence of

trigger

When address (A1, A0)=(1, 0) and data (D6, D5, D4, D3, D2,

D1, D0)=(0, 1, 1, 0, 1, 0, 0), CKO with the first rise after oc-

currence of a trigger is output and then CKO stops.

However, this mode is not available when D1=1 in trigger

edge setting. Set a wide TR so that TR sync edge is entered

200ns or more after CKO stops.

1) 200ns or more required

2) Note: tss (CKO, CKOB, PULSE) is defined by input clock

width "L" +

α. In addition, the value of α denotes IC internal

delay, and the values of

α and tss are definite unless tem-

perature, Vcc, etc. are changed, and tss variations at that

time is defined as

∆t (sync accuracy: jitter).

CKO/PLLO output frequency range

The M66238 requires an internal VCO oscillator frequency of

25MHz to 50MHz.

Settings of dividing ratio K of 12-bit divider and dividing ratio

N of 15-bit counter are required in order to determine the in-

ternal VCO oscillator frequency. The relation between the

settings and the internal VCO oscillator frequency is shown

below.

Oscillator frequency

3) Note: Setting of fin/K

≥100kHz is recommended in consid-

eration of the frequency accuracy characteristics of PLL out-

put.

Therefore, set the division ratio K of the 12 bit divider and the

division ratio N of the 15 bit counter to meet the following con-

ditions:

25MHz

≤fvco≤50MHz

In addition, for PLLO and CKO, setting the division ratios of

the sync/division circuit (synchronous clock generating area)

to 1/1, 1/2, 1/4, 1/8, 1/16, 1/32 will allow the frequencies of

0.78Hz - 50MHz to be accommodated.

fin

× N

fVCO =

(MHz)

∑ (Dk × 2k)

k = 0

∑ (Dn × 2n–12)

n = 12

tw(TR)

1st

tss(CKO)

200ns or more required

tss(CKOB)

tss(PULSE)

tw(PULSE)

∆t

CKO

CKOB

PULSE

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