STNRGPF02TR datasheet(12/43 Pages) STMICROELECTRONICS

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Figure 11. Driving & interleaving

Once the device is programmed as soon as the device is supplied the following sequence to generate the PWM

starts:

•

Pin n. 2 emits CLOCK signal at selected switching frequency. This pin must be connected to ENABLE pin (n.

6) and the clock signal will be internally used in order to enable the PWM GENERATION block. The

ENABLE signal moreover is used to avoid undesired commutations also when high level of noise is present.

•

The PWM0 signal trigger the SYNCR pin (pin 7) and internally the SET GENERATOR BLOCK will generate

the SET pulse with an out of phase of 180º (for a correct interleaving) respect the PWM0 signal. The SET

will fix the “ON” instant of PWM1 signal.

•

The SET signal comes out from the SET_O pin and will enter in the SET inputs (pin 18 SET_I) of an internal

FLIP FLOP.

The internal FLIP FLOP receives the SET from pin 18 and the RESET signal from PWM GENERATOR BLOCK

and in this way it is able to generate the PW1 with the right out of phase respect to PWM0. The PWM1 comes out

from the pin 16 “PWM1”.

3.5

Programming section

Device programming is done by using: a PC with a dedicated loader software (STSW-STNRGPF01), a FTDI

cable and an adapter board (See Figure 12.)

STNRGPF02, STNRGPF12

Programming section

DS12895 - Rev 2

page 12/43

STNRGPF02TR Datasheet(PDF) 12 Page - STMicroelectronics