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XRK69774 Datasheet(PDF) 7 Page - Exar Corporation

Part # XRK69774
Description  1:14 LVCMOS PLL CLOCK GENERATOR
PDF  11 Pages
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRK69774 Datasheet(HTML) 7 Page - Exar Corporation

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PRELIMINARY
XRK69774
7
REV. P1.0.1
1:14 LVCMOS PLL CLOCK GENERATOR
2.0
CONFIGURATION TABLES
TABLE 6: FUNCTION CONTROLS
CONTROL PIN
DEFAULT
LOGIC 0
LOGIC 1
MR/OE
1
Resets the output divide circuitry and serial
interface, tri-states all outputs
Enables all outputs - normal operation
PLL_EN
1
PLL bypass mode enabled. This is a test
mode in which the reference clock is provided
to the output dividers in place of the VCO
output.
PLL enabled - normal operation
STOP_CLK
1
QA[4:0], QB[4:0] and QC[3:0] outputs disabled
in Low state.
Outputs enabled, normal operation
CLK_SEL
0
CLK0 selected as PLL reference
CLK1 selected
VCO_SEL
0
VCO ÷ 2
VCO ÷ 4
TABLE 7: BANK OUTPUT DIVIDER CONTROLS
INPUT
OUTPUT
INPUT
OUTPUT
INPUT
OUTPUT
VC0_SEL
FSEL_A
QA[4:0]
VCO_SEL
FSEL_B
QB[4:0]
VC0_SEL
FSEL_C
QC[3:0]
0
0
÷4
0
0
÷4
0
0
÷8
0
1
÷8
0
1
÷8
0
1
÷12
1
0
÷8
1
0
÷8
1
0
÷16
1
1
÷16
1
1
÷16
1
1
÷24
TABLE 8: FEEDBACK DIVIDER CONTROL
VCO_SEL
FSEL_FB1
FSEL_FB0
QFB
0
0
0
÷8
0
0
1
÷16
0
1
0
÷12
0
1
1
÷24
1
0
0
÷16
1
0
1
÷32
1
1
0
÷24
1
1
1
÷48



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