R

EM6607

Copyright © 2005, EM Microelectronic-Marin SA

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7.3

PortC

This port can be configured as either input or output (but it is not bitwise selectable). When in input mode it implements the

identical interrupt functions as PortA. The PortC register is used to read data when input mode and to write data when in

output mode. Input mode is set by writing 0 in the I/O control bit CIOPC in register CPIOB, the input becomes high

impedance. On each terminal controlled Pull-Up/Down resistor can be selected by metal option, which are active only when

port is input. When we want to use internal Strong pull-up resistor also when PortC terminal is declared as N-channel open

drain output and internal pull-up resistor is used to pull up the output (not-controlled pull-up). This is a special option “sod” =

strong pull-up for Open drain- active all the time (when terminal is input or output).

The output mode is selected by writing 1 to CIOPC bit, and the terminal follows the bits in the PortC register. When PortC is

used as an input, interrupt functions as described for PortA can be enabled. Input to the interrupt logic can be direct or via a

debounced input. With the debPCN bit at 0 in the Option register all the PortC inputs are debounced and with the debPCN

bit at 1 none of the PortC inputs are debounced. MPortC is the interrupt mask register for this port and IRQpC is the portC

interrupt request register. See also section 9.

By writing the PA&C bit in the CPIOB data register it is

possible to combine PortA and PortC interrupt requests

(logic AND) as shown in Table 17

At initial reset, the CPIOC control register is set to 0, and the

port is in input mode. The MPortC register is also set to 0,

therefore disabling interrupts.

Table 18.

Ports A&C Interrupt

IRQPA

IRQPC

PA&C

Request to CPU

0

0

X

No

0

1

0

Yes

1

0

0

Yes

1

1

0

Yes

0

1

1

No

1

0

1

No

1

1

1

Yes

7.3.1

PortC registers

Table 19.

PortC input/output register - PortC

Bit

Name

Reset

R/W

Description

3

PC3

-

R/W

PC3 I/O data

2

PC2

-

R /W

PC2 I/O data

1

PC1

-

R/W

PC1 I/O data

0

PC0

-

R /W

PC0 I/O data

Table 20.

PortC Interrupt request register - IRQpC

Bit

Name

Reset

R/W

Description

3

IRQpc3

0

R

input PC3 interrupt request flag

2

IRQpc2

0

R

input PC2 interrupt request flag

1

IRQpc1

0

R

input PC1 interrupt request flag

0

IRQpc0

0

R

input PC0 interrupt request flag

Table 21.

PortC interrupt mask register - MportC

Bit

Name

Reset

R/W

Description

3

MPC3

0

R/W

interrupt mask for input PC3

2

MPC2

0

R/W

interrupt mask for input PC2

1

MPC1

0

R/W

interrupt mask for input PC1

0

MPC0

0

R/W

interrupt mask for input PC0