IMX8MPCEC datasheet(49/111 Pages) NXP

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Electrical characteristics

i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

3.8.2.2

eMMC5.1/SD3.0 (dual data rate) AC timing

Figure 16 depicts the timing of eMMC5.1/SD3.0 (DDR). Table 40 lists the eMMC5.1/SD3.0 (DDR)

timing characteristics. Be aware that only DATA is sampled on both edges of the clock (not applicable to

CMD).

Figure 16. eMMC5.1/SD3.0 (DDR) timing

SD4

Clock Rise Time

tTLH

—3

SD5

Clock Fall Time

tTHL

—3

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)

SD6

uSDHC Output Delay

tOD

6.6

3.6

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)

SD7

uSDHC Input Setup Time

tISU

2.5

—

SD8

uSDHC Input Hold Time4

tIH

1.5

—

1 In Low-Speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

2 In Normal (Full) -Speed mode for SD/SDIO card, clock frequency can be any value between 0 – 25 MHz. In High-speed mode,

clock frequency can be any value between 0

– 50 MHz.

3 In Normal (Full) -Speed mode for MMC card, clock frequency can be any value between 0 – 20 MHz. In High-speed mode,

clock frequency can be any value between 0

– 52 MHz.

4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

Table 40. eMMC5.1/SD3.0 (DDR) interface timing specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency (eMMC5.1 DDR)

fPP

052

MHz

SD1

Clock Frequency (SD3.0 DDR)

fPP

050

MHz

Table 39. SD3.0/eMMC5.1 (SDR) interface timing specification (continued)

Parameter

Symbols

Min

Max

Unit

SD1

SD2

SD3

Output from eSDHCv3 to card

Input from card to eSDHCv3

SDx_DATA[7:0]

SDx_CLK

SD4

SD2

......

SDx_DATA[7:0]

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