STM32H7B0IB datasheet(146/205 Pages) STMICROELECTRONICS

146 / 205 page

•

Data formats: 14 bits

•

Capacitive load CL=30 pF

•

Measurement points are done at CMOS levels: 0.5VDD

•

Output speed is set to OSPEEDRy[1:0] = 11

•

VOS level set to VOS0

Table 107. DCMI characteristics

Symbol

Parameter

Min(1)

Max(1)

Unit

Frequency ratio DCMI_PIXCLK/fHCLK

0.4

DCMI_PIXCLK

Pixel Clock input

MHz

Dpixel

Pixel Clock input duty cycle

tsu(DATA)

Data input setup time

2.5

th(DATA)

Data hold time

tsu(HSYNC),

tsu(VSYNC)

DCMI_HSYNC/ DCMI_VSYNC input setup time

th(HSYNC),

th(VSYNC)

DCMI_HSYNC/ DCMI_VSYNC input hold time

1. Guaranteed by design.

Figure 52. DCMI timing diagram

DCMI_PIXCLK

tsu(VSYNC)

tsu(HSYNC)

DCMI_HSYNC

DCMI_VSYNC

DATA[0:13]

1/DCMI_PIXCLK

th(HSYNC)

tsu(DATA) th(DATA)

6.3.32

PSSI interface characteristics

Unless otherwise specified, the parameters given in Table 108 and 109for PSSI are derived from tests performed

under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 20. General

operating conditions and Section 6.3.1 , with the following configuration:

•

PSSI_PDCK polarity: falling

•

PSSI_RDY and PSSI_DE polarity: low

•

Bus width : 16 lines

•

DATA width : 32 bits

•

Capacitive load C=30 pF

•

Measurement points are done at CMOS levels: 0.5VDD

•

Output speed is set to OSPEEDRy[1:0] = 11

STM32H7B0xB

Operating conditions

DS13196 - Rev 7

page 146/205

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