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ICS9LPRS477C Datasheet(PDF) 11 Page - Renesas Technology Corp |
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ICS9LPRS477C Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 25 page  IDT® Programmable System Clock Chip for ATI RD790-K8TM Based Systems 1393—01/28/14 9LPRS477C Programmable System Clock Chip for ATI RD790 - K8TM based Systems 11 SMBus Table: ATIG Frequency Select Register Byte 5 Name Control Function Type 0 1 Default Bit 7 ATIG PLL TBEN ATIG PLL Turbo Enable RW Disable Enable 0 Bit 6 CPU PLL TBEN CPU PLL Turbo Enable RW Disable Enable 0 Bit 5 SRC PLL TBEN SRC PLL Turbo Enable RW Disable Enable 0 Bit 4 DISABLE_ORT Disable O vershoot R eduction T echnology during CPU PLL M/N Programming RW ENABLE ORT DISABLE ORT 0 Bit 3 ATIG_FS3 ATIG Frequency Select RW 1 Bit 2 ATIG_FS2 ATIG Frequency Select RW 1 Bit 1 ATIG_FS1 ATIG Frequency Select RW 1 Bit 0 ATIG_FS0 ATIG Frequency Select LSB RW 1 SMBus Table: SB_SRC Frequency Select Register Byte 6 Name Control Function Type 0 1 Default Bit 7 ATIG SSEN ATIG Spread Enable RW Disable Enable 0 Bit 6 SB_SRC/CPU SSEN SB_SRC/CPU Spread Enable RW Disable Enable 0 Bit 5 SRC SSEN SRC Spread Enable RW Disable Enable 0 Bit 4 SB_SRC_FS4 SB_SRC Frequency Select MSB RW 0 Bit 3 SB_SRC_FS3 SB_SRC Frequency Select RW 1 Bit 2 SB_SRC_FS2 SB_SRC Frequency Select RW 1 Bit 1 SB_SRC_FS1 SB_SRC Frequency Select RW 1 Bit 0 SB_SRC_FS0 SB_SRC Frequency Select LSB RW 1 SMBus Table: Device ID register Byte 7 Name Control Function Type 0 1 Default Bit 7 Device ID7 R x Bit 6 Device ID6 R x Bit 5 Device ID5 R x Bit 4 Device ID4 R x Bit 3 Device ID3 R x Bit 2 Device ID2 R x Bit 1 Device ID1 R x Bit 0 Device ID0 R x SMBus Table: Vendor & Revision ID Register Byte 8 Name Control Function Type 0 1 Default Bit 7 RID3 R - - 0 Bit 6 RID2 R - - 0 Bit 5 RID1 R - - 1 Bit 4 RID0 R - - 1 Bit 3 VID3 R - - 0 Bit 2 VID2 R - - 0 Bit 1 VID1 R - - 0 Bit 0 VID0 R - - 1 SMBus Table: WatchDog Timer Control Register Byte 9 Name Control Function Type 0 1 Default Bit 7 HWD_EN Watchdog Hard Alarm Enable RW Disable and Reload Hartd Alarm Timer, Clear WD Hard status bit. Enable Timer 0 Bit 6 SWD_EN Watchdog Soft Alarm Enable RW Disable Enable 0 Bit 5 WD Hard Status WD Hard Alarm Status R Normal Alarm X Bit 4 WD Soft Status WD Soft Alarm Status R Normal Alarm X Bit 3 WDTCtrl Watch Dog Alarm Time base Control RW 290ms Base 1160ms Base 0 Bit 2 HWD2 WD Hard Alarm Timer Bit 2 RW 1 Bit 1 HWD1 WD Hard Alarm Timer Bit 1 RW 1 Bit 0 HWD0 WD Hard Alarm Timer Bit 0 RW 1 VENDOR ID REVISION ID See ATIG Frequency Select Table These bits represent the number of Watch Dog Time Base Units that pass before the Watch Alarm expires. Default is 7 X 290ms = 2s. Device ID 75 hex for 9LPRS477 See SB_SRC Frequency Select Table Note: SB_SRC and CPU Clocks are synchronous. Changing this frequency w ill alter the SB_SRC and CPU frequency by the same percentage. |
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