IDT®

Programmable System Clock Chip for ATI RD790-K8TM Based Systems

1393—01/28/14

9LPRS477C

Programmable System Clock Chip for ATI RD790 - K8TM based Systems

19

AC Electrical Characteristics - Low-Power DIF Outputs: CPUKG and HTT

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Crossing Point Variation

∆V

CROSS

Single-ended Measurement

140

mV

1,2,5

Frequency

f

Spread Specturm On

198.8

200

MHz

1,3

Long Term Accuracy

ppm

Spread Specturm Off

-300

+300

ppm

1,11

Rising Edge Slew Rate

S

RISE

Differential Measurement

0.5

10

V/ns

1,4

Falling Edge Slew Rate

S

FALL

Differential Measurement

0.5

10

V/ns

1,4

Slew Rate Variation

t

SLVAR

Single-ended Measurement

20

%

1

CPU, DIF HTT

Jitter - Cycle to Cycle

CPUJ

C2C

Differential Measurement

150

ps

1,6

Accumulated Jitter

t

JACC

See Notes

1

ns

1,7

Peak to Peak Differential

Voltage

V

D(PK-PK)

Differential Measurement

400

2400

mV

1,8

Differential Voltage

V

D

Differential Measurement

200

1200

mV

1,9

Duty Cycle

D

CYC

Differential Measurement

45

55

%

1

Amplitude Variation

∆V

D

Change in V

D DC cycle to cycle

-75

75

mV

1,10

CPU[1:0] Skew

CPU

SKEW10

Differential Measurement

100

ps

1

*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 2pF w ith Rs = 0Ω (unless otherw ise specified)

1Guaranteed by design and characterization, not 100% tested in production.

3Minimum Frequency is a result of 0.5% dow n spread spectrum

6 Max difference of t

CYCLE betw een any tw o adjacent cycles.

8 VD(PK-PK) is the overall magnitude of the differential signal.

11 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz

10 The difference in magnitude of tw o adjacent VD_DC measurements. VD_DC is the stable post overshoot and ring-back part of the

signal.

2Single-ended measurement at crossing point. Value is maximum – minimum over all time. DC value of common mode is not important due

to the blocking cap.

5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and

falling edge of CLK#. It is measured using a +/-75mV w indow centered on the average cross point w here CLK meets CLK#.

4Differential measurement through the range of ±100 mV, differential signal must remain monotonic and w ithin slew rate spec w hen

crossing through this region.

9 VD(min) is the amplitude of the ring-back differential measurement, guaranteed by design, that ring-back w ill not cross 0V VD.

VD(max) is the largest amplitude allow ed.

7 Accumulated tjc.over a 10µs time period, measured w ith JIT2 TIE at 50ps interval.