ISL6324A datasheet(21/39 Pages) RENESAS

21 / 39 page

ISL6324A Hybrid SVI/PVI with I2C

FN6880 Rev 1.00

Page 21 of 39

May 14, 2010

If ISEN4- is tied to VCC, the controller will configure the

channel firing order and timing for 3-phase operation. If ISEN3-

and ISEN4- are tied to VCC, the controller will set the channel

firing order and timing for 2-phase operation (see “PWM

Operation” on page 12 for details). If Channel 4 and/or

Channel 3 are disabled, then the corresponding PWMn and

ISENn+ pins may be left unconnected

Soft-Start Output Voltage Targets

Once the POR and Phase Detect blocks and enable

comparator are satisfied, the controller will begin the soft-start

sequence and will ramp the CORE and NB output voltages up

to the SVI interface designated target level if the controller is

set SVI mode. If set to PVI mode, the North Bridge regulator is

disabled and the core is soft started to the level designated by

the parallel VID code.

SVI MODE

Prior to soft-starting both CORE and NB outputs, the ISL6324A

must check the state of the SVI interface inputs to determine

the correct target voltages for both outputs. When the

controller is enabled, the state of the VFIXEN, SVD and SVC

inputs are checked and the target output voltages set for both

CORE and NB outputs are set by the DAC (see “Serial VID

Interface (SVI)” on page 15). These targets will only change if

the EN signal is pulled low or after a POR reset of VCC.

Soft-Start

The soft-start sequence is composed of three periods, as

shown in Figure 11. At the beginning of soft-start, the DAC

immediately obtains the output voltage targets for both outputs

by decoding the state of the SVI or PVI inputs. A 100µs fixed

delay time, TDA, proceeds the output voltage rise. After this

delay period the ISL6324A will begin ramping both CORE and

NB output voltages to the programmed DAC level at a fixed

rate of 3.25mV/µs. The amount of time required to ramp the

output voltage to the final DAC voltage is referred to as TDB,

and can be calculated as shown in Equation 17.

After the DAC voltage reaches the final VID setting,

VDDPWRGD will be set to high.

Pre-Biased Soft-Start

The ISL6324A also has the ability to start up into a pre-charged

output, without causing any unnecessary disturbance. The FB

pin is monitored during soft-start, and should it be higher than

the equivalent internal ramping reference voltage, the output

drives hold both MOSFETs off.

Once the internal ramping reference exceeds the FB pin

potential, the output drives are enabled, allowing the output to

ramp from the pre-charged level to the final level dictated by the

DAC setting. Should the output be pre-charged to a level

exceeding the DAC setting, the output drives are enabled at the

end of the soft-start period, leading to an abrupt correction in the

output voltage down to the DAC-set level.

Both CORE and NB output support start up into a pre-charged

output.

(EQ. 17)

TDB

VDAC

3.25 10

–



------------------------------

FIGURE 11. SOFT-START WAVEFORMS

100µs/DIV

VDDPWRGD

TDA

TDB

VCORE

VNB

400mV/DIV

5V/DIV

FIGURE 12. SOFT-START WAVEFORMS FOR

ISL6324A-BASED MULTI-PHASE CONVERTER

OUTPUT PRECHARGED

BELOW DAC LEVEL

OUTPUT PRECHARGED

ABOVE DAC LEVEL

VCORE

400mV/DIV

5V/DIV

100µs/DIV

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