MPC9331 REVISION 7 March 11, 2016

3

©2016 Integrated Device Technology, Inc.

MPC9331 Data Sheet

3.3 V 1:6 LVCMOS PLL CLOCK GENERATOR

Figure 2. MPC9331 32-Lead Package Pinout (Top View)

Table 1. Pin Configuration

Pin

I/O

Type

Function

CCLK

Input

LVCMOS

PLL reference clock signal

PCLK, PCLK

Input

LVPECL

Differential PECL reference clock signal

FB_IN

Input

LVCMOS

PLL feedback signal input, connect to an output

FB_SEL

Input

LVCMOS

Feedback select

REF_SEL

Input

LVCMOS

Reference clock select

PWR_DN

Input

LVCMOS

Output frequency and power down select

FSELA

Input

LVCMOS

Frequency divider select for bank A outputs

FSELB

Input

LVCMOS

Frequency divider select for bank B outputs

FSELC

Input

LVCMOS

Frequency divider select for bank C outputs

PLL_EN

Input

LVCMOS

PLL enable/disable

CLK_STOP0-1

Input

LVCMOS

Clock output enable/disable

OE/MR

Input

LVCMOS

Output enable/disable (high-impedance tristate) and device reset

QA0-1, QB0-1, QC0-1

Output

LVCMOS

Clock outputs

GND

Supply

Ground

Negative power supply (GND)

VCC_PLL

Supply

VCC

PLL positive power supply (analog power supply). It is recommended to use external RC filter

for the analog power supply pin VCC_PLL. Please see applications section for details.

VCC

Supply

VCC

Positive power supply for I/O and core. All VCC pins must be connected to the positive power

supply for correct operation

GND

QA1

QA0

V

CC

FSELA

FSELB

FSELC

GND

QC1

QC0

V

CC

FB_IN

CLK_STOP1

25

26

27

28

29

30

31

32

15

14

13

12

11

10

9

12

3

4

5

6

78

24

23

22

21

20

19

18

17

16

MPC9331

NC

CLK_STOP0

NC

It is recommended to use an external RC filter for the analog VCC_PLL power supply pin. Please see Applications Information section for details.