MPC9331 REVISION 7 March 11, 2016

8

©2016 Integrated Device Technology, Inc.

MPC9331 Data Sheet

3.3 V 1:6 LVCMOS PLL CLOCK GENERATOR

Table 8. MPC9331 Example Configurations (Internal Feedback: FB_SEL = 0)

fref(1) [MHz]

1. fref is the input clock reference frequency (CCLK or PCLK).

PWR_DN

FSELA

FSELB

FSELC

QA[0:1]:fref ratio

QB[0:1]:fref ratio

QC[0:1]:fref ratio

25.0 – 60.0

0

0

0

0

fref

 4

(100-240 MHz) fref

 4

(100-240 MHz) fref

 2

(50-120 MHz)

0

0

0

1

fref

 4

(100-240 MHz) fref

 4

(100-240 MHz) fref

43

(33.3-80 MHz)

0

0

1

0

fref

 4

(100-240 MHz) fref

 2

(50-120 MHz) fref

 2

(50-120 MHz)

0

0

1

1

fref

 4

(100-240 MHz) fref

 2

(50-120 MHz) fref

43

(33.3-80 MHz)

0

1

0

0

fref

 2

(50-120 MHz) fref

 4

(100-240 MHz) fref

 2

(50-120 MHz)

0

1

0

1

fref

 2

(50-120 MHz) fref

 4

(100-240 MHz) fref

43

(33.3-80 MHz)

0

1

1

0

fref

 2

(50-120 MHz) fref

 2

(50-120 MHz) fref

 2

(50-120 MHz)

0

1

1

1

fref

 2

(50-120 MHz) fref

 2

(50-120 MHz) fref

43

(33.3-80 MHz)

1

0

0

0

fref

 2

(50-120 MHz) fref

 2

(50-120 MHz) fref

(25.0-60 MHz)

1

0

0

1

fref

 2

(50-120 MHz) fref

 2

(50-120 MHz) fref

23

(16.67-40 MHz)

1

0

1

0

fref

 2

(50-120 MHz) fref

(25.0-60 MHz) fref

(25.0-60 MHz)

1

0

1

1

fref

 2

(50-120 MHz) fref

(25.0-60 MHz) fref

23

(16.67-40 MHz)

1

1

0

0

fref

(25.0-60 MHz) fref

 2

(50-120 MHz) fref

(25.0-60 MHz)

1

1

0

1

fref

(25.0-60 MHz) fref

 2

(50-120 MHz) fref

23

(16.67-40 MHz)

1

1

1

0

fref

(25.0-60 MHz) fref

(25.0-60 MHz) fref

(25.0-60 MHz)

1

1

1

1

fref

(25.0-60 MHz) fref

(25.0-60 MHz) fref

23

(16.67-40 MHz)

Table 9. MPC9331 Example Configurations (External Feedback and PWR_DN = 0)

PLL

Feedback

fref(1)

[MHz]

1. fref is the input clock reference frequency (CCLK or PCLK).

FSELA FSELB FSELC

QA[0:1]:fref ratio

QB[0:1]:fref ratio

QC[0:1]:fref ratio

VCO

 2(2)

2. QAx connected to FB_IN and FSELA=0, PWR_DN=0.

100 – 240

0

0

0

fref

(100-240 MHz) fref

(100-240 MHz) fref

 2

(50-120 MHz)

0

0

1

fref

(100-240 MHz) fref

(100-240 MHz) fref

 3

(33.3-80 MHz)

0

1

0

fref

(100-240 MHz) fref

 2

(50-120 MHz) fref

 2

(50-120 MHz)

0

1

1

fref

(100-240 MHz) fref

 2

(50-120 MHz) fref

 3

(33.3-80 MHz)

VCO

 4(3)

3. QAx connected to FB_IN and FSELA=1, PWR_DN=0.

50 –120

1

0

0

fref

(50-120 MHz) fref

2

(100-240 MHz) fref

(50-120 MHz)

1

0

1

fref

(50-120 MHz) fref

2

(100-240 MHz) fref

23

(33.3-80 MHz)

1

1

0

fref

(50-120 MHz) fref

(100-240 MHz) fref

(50-120 MHz)

1

1

1

fref

(50-120 MHz) fref

(100-240 MHz) fref

2  3

(33.3-80 MHz)

VCO

 6(4)

4. QCx connected to FB_IN and FSELC=1, PWR_DN=0.

33.3 – 80

0

0

1

fref

3

(100-240 MHz) fref

3

(100-240 MHz) fref

(33.3-80 MHz)

0

1

1

fref

3

(100-240 MHz) fref

3  2

(50-120 MHz) fref

(33.3-80 MHz)

1

0

1

fref

3  2 (50-120 MHz) fref 3

(100-240 MHz) fref

(33.3-80 MHz)

1

1

1

fref

3  2 (50-120 MHz) fref 3  2

(50-120 MHz) fref

(33.3-80 MHz)

Table 10. MPC9331 Example Configurations (External Feedback and PWR_DN = 1)

PLL

Feedback

fref(1)

[MHz]

FSELA

FSELB

FSELC

QA[0:1]:fref ratio

QB[0:1]:fref ratio

QC[0:1]:fref ratio

VCO

 8(2)

25.0 – 60.0

1

0

0

fref

25-60 MHz) fref

2

(50-120 MHz)

fref

(2.25-60 MHz)

101

fref

(25-60 MHz) fref

2

(50-120 MHz)

fref

23

(16.6-40 MHz)

110

fref

(25-60 MHz) fref

(25-60 MHz)

fref

(25-60 MHz)

111

fref

(25-60 MHz) fref

(25-60 MHz)

fref

23

(16.6-40 MHz)

VCO

 12(3) 16.67 – 40

0

0

1

fref

3

(50-120 MHz) fref

3

(50-120 MHz)

fref

(16.67-40 MHz)

011

fref

3

(50-120 MHz) fref

3  2 (25-60 MHz) fref

(16.67-40 MHz)

101

fref

3  2 (25-60 MHz) fref 3

(50-120 MHz)

fref

(16.67-40 MHz)

111

fref

3  2 (25-60 MHz) fref 3  2 (25-60 MHz) fref

(16.67-40 MHz)

1. fref is the input clock reference frequency (CCLK or PCLK).

2. QAx connected to FB_IN and FSELA=1, PWR_DN=1.

3. QCx connected to FB_IN and FSELC=1, PWR_DN=1.