MPC9773 datasheet(13/22 Pages) RENESAS

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MPC9773 REVISION 6 MARCH 16, 2016

MPC9773 Data Sheet

3.3 V 1:12 LVCMOS PLL CLOCK GENERATOR

Due to the statistical nature of I/O jitter, an RMS value (1

) is specified. I/O jitter numbers for other confidence factors

(CF) can be derived from Table 12.

The feedback trace delay is determined by the board

layout and can be used to fine-tune the effective delay

through each device.

Due to the frequency dependence of the static phase

offset and I/O jitter, using Figure 9 to Figure 11 to predict a

maximum I/O jitter and the specified t(

 parameter relative to

the input reference frequency results in a precise timing

performance analysis.

In the following example calculation an I/O jitter confidence

factor of 99.7% (

 3) is assumed, resulting in a worst-case

timing uncertainty from the common input reference clock to

any output of –455 ps to +455 ps relative to CCLK (PLL

feedback =

8, reference frequency = 50 MHz, VCO

frequency = 400 MHz, I/O jitter = 13 ps RMS max., static

phase offset t() =  166 ps):

tSK(PP) = [–166ps...166ps] + [–250ps...250ps] +

[(13ps

 –3)...(13ps  3)] + t

PD, LINE(FB)

tSK(PP) = [–455ps...455ps] + tPD, LINE(FB)

Figure 9. MPC9773 I/O Jitter

Figure 10. MPC9773 I/O Jitter

Figure 11. MPC9773 I/O Jitter

Driving Transmission Lines

The MPC9773 clock driver was designed to drive high

speed signals in a terminated transmission line environment.

To provide the optimum flexibility to the user, the output

drivers were designed to exhibit the lowest impedance

possible. With an output impedance of less than 20

 the

drivers can drive either parallel or series terminated

transmission lines. For more information on transmission

lines the reader is referred to Freescale Semiconductor

application note AN1091. In most high-performance clock

networks point-to-point distribution of signals is the method of

choice. In a point-to-point scheme, either series terminated or

parallel terminated transmission lines can be used. The

parallel technique terminates the signal at the end of the line

with a 50-

 resistance to V

CC 2.

Table 12. Confidence Factor CF

Probability of Clock Edge

within the Distribution

 1

0.68268948

 2

0.95449988

 3

0.99730007

 4

0.99993663

 5

0.99999943

 6

0.99999999

VCO frequency [MHz]

200

250

300

350

400

450 480

160

140

120

100

FB =

32

FB =

16

FB =

8

FB =

4

Maximum I/O Phase Jitter versus Frequency Parameter:

PLL Feedback Divider FB

VCO frequency [MHz]

200

250

300

350

400

450 480

120

100

FB =

12

FB =

24

Maximum I/O Phase Jitter versus Frequency Parameter:

PLL Feedback Divider FB

FB =

6

VCO frequency [MHz]

200

250

300

350

400

450

480

140

120

100

FB =

20

FB =

10

FB =

40

Maximum I/O Phase Jitter versus Frequency Parameter:

PLL Feedback Divider FB

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