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MPC9773 Datasheet(PDF) 2 Page - Renesas Technology Corp |
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MPC9773 Datasheet(HTML) 2 Page - Renesas Technology Corp |
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2 / 22 page  MPC9773 REVISION 6 MARCH 16, 2016 2 ©2016 Integrated Device Technology, Inc. MPC9773 Data Sheet 3.3 V 1:12 LVCMOS PLL CLOCK GENERATOR Figure 1. MPC9773 Logic Diagram Figure 2. MPC9773 52-Lead Package Pinout (Top View) PLL 4, 6, 8, 12 0 1 1 0 1 0 1 0 QFB QSYNC 12 3 2 2 2 All input resistors have a value of 25 k 1 0 PCLK PCLK CCLK0 CCLK1 FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] INV_CLK QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC0 QC1 Bank A Bank B Bank C Clock Stop VCO Ref FB SYNC PULSE 4, 6, 8, 10 12, 16, 20 2, 4, 6, 8 4, 6, 8, 10 QC2 QC3 FSEL_FB[0:2] STOP_DATA STOP_CLK MR/OE CCLK_SEL REF_SEL FB_IN VCO_SEL PLL_EN VCC 200–485 MHz CLK Stop CLK Stop CLK Stop CLK Stop CLK Stop VCC VCC VCC 2 1 Power-On Reset FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 QA3 VCC QA2 GND QA1 VCC QA0 GND VCO_SEL FSEL_FB1 QSYNC GND QC0 VCC QC1 FSEL_C0 FSEL_C1 QC2 VCC QC3 GND INV_CLK 40 41 42 43 44 45 46 47 48 49 50 51 52 25 24 23 22 21 20 19 18 17 16 15 14 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 26 MPC9773 |
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