ISL81601 datasheet(45/54 Pages) RENESAS

45 / 54 page

FN9299 Rev.3.1

Page 45 of 53

May 27, 2021

ISL81601

7. Layout Guidelines

Layout Guidelines

Careful attention to layout requirements is necessary for successful implementation of an ISL81601 based DC/DC

converter. The ISL81601 switches at a very high frequency, so the switching times are very short. At these switching

frequencies, even the shortest trace has significant impedance. Also, the peak gate drive current rises significantly in an

extremely short time. Transition speed of the current from one device to another causes voltage spikes across the

interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, generate EMI,

and increase device voltage stress and ringing. Careful component selection and proper Printed Circuit Board (PCB)

layout minimize the magnitude of these voltage spikes.

The three sets of critical components in a DC/DC converter using the ISL81601 are the following:

• the controller

• the switching power components

• the small signal components

The switching power components are the most critical from a layout point of view because they switch a large amount

of energy, which tends to generate a large amount of noise. The critical small signal components are those connected to

sensitive nodes or those supplying critical bias currents. A multilayer PCB is recommended.

7.1

Layout Considerations

(1) The input capacitors, buck FETs, inductor, boost FETs, and output capacitor should be placed first. Isolate

these power components on dedicated areas of the board with their ground terminals adjacent to one another.

Place the input and output high frequency decoupling ceramic capacitors very close to the MOSFETs.

(2) If signal components and the IC are placed in a separate area to the power train, use full ground planes in the

internal layers with shared SGND and PGND to simplify the layout design. Otherwise, use separate ground

planes for the power ground and the small signal ground. Connect the SGND and PGND together close to the

IC. DO NOT connect them together anywhere else.

(3) Keep the loop formed by the input capacitor, the buck top FET, and the buck bottom FET as small as possible.

Also, keep the loop formed by the output capacitor, the boost top FET, and the boost bottom FET as small as

possible.

(4) Ensure the current paths from the input capacitor to the buck FETs, the power inductor, the boost FETs, and

the output capacitor are as short as possible with maximum allowable trace widths.

(5) Place the PWM controller IC close to the lower FETs. The low-side FETs gate drive connections should be

short and wide. Place the IC over a quiet ground area. Avoid switching ground loop currents in this area.

(6) Place the VDD bypass capacitor very close to the VDD pin of the IC and connect its ground end to the PGND

pin. Connect the PGND pin to the ground plane by a via. Do not directly connect the PGND pin to the SGND

EPAD.

(7) Place the gate drive components (BOOT diodes and BOOT capacitors) together near the controller IC.

(8) Place the output capacitors as close to the load as possible. Use short, wide copper regions to connect output

capacitors to load to avoid inductance and resistances.

(9) Use copper filled polygons or wide short traces to connect the junction of the buck or boost upper FET, buck

or boost lower FET, and output inductor. Also keep the buck and boost PHASE nodes connection to the IC

short. DO NOT oversize the copper islands for the PHASE nodes. Because the phase nodes are subjected to

very high dv/dt voltages, the stray capacitor formed between these islands and the surrounding circuitry tends

to couple switching noise.

(10) Route all high speed switching nodes away from the control circuitry.

(11) Create a separate small analog ground plane near the IC. Connect the SGND pin to this plane. All small signal

grounding paths including feedback resistors, current monitoring resistors and capacitors, soft-starting

capacitors, loop compensation capacitors and resistors, and EN pull-down resistors should be connected to

this SGND plane.

ISL81601 Datasheet(PDF) 45 Page - Renesas Technology Corp

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