ISL81601 datasheet(12/54 Pages) RENESAS

12 / 54 page

FN9299 Rev.3.1

Page 12 of 53

May 27, 2021

ISL81601

2. Pin Information

VIN

Tie this pin to the input rail using a 5-10Ω resistor. It provides power to the internal LDO for VDD.

Decouple this pin with a small ceramic capacitor (10nF to 1µF) to ground.

CS+

Input current sense signal positive input pin.

CS-

Input current sense signal negative input pin.

EN/

UVLO

This pin provides enable/disable and accurate UVLO functions. The output is disabled when the pin

is pulled to ground. When the voltage on the pin reaches 1.3V, the VDD and VCC5V LDOs become

active. When the voltage on the pin reaches 1.8V, the PWM modulator is enabled. When the pin is

floating, it is enabled in default by internal pull-up.

IMON_IN

Input current monitor. The current from this pin is proportional to the differential voltage between the

CS+ and CS- pins. Connect a resistor and capacitor network between the pin and SGND to make

the pin voltage proportional to the average input current. When the pin voltage reaches 1.2V, the

internal average current limit loop reduces the output voltage to keep the input current constant

when constant current OCP mode is set or the converter shuts down when hiccup OCP mode is set.

When the input current monitor function is not used, tie this pin to VCC5V or SGND to set up the

phase shift for interleaving parallel operation.

CLKEN

DE mode burst operation off state enable signal. The pin is pulled up to 5V by an internal 250k

resistor in PWM and DE modes and burst mode on state. It is pulled low in Burst mode off state. The

pull-down MOSFET rDS(ON) resistance is about 4.5k. Connect this pin together in multi-chip parallel

operation application to sync all the chips together for the burst operation.

-11

SGND

EPAD

Small-signal ground common to all control circuitries. Route this pin separately from the high current

ground (PGND). SGND and PGND can be tied together if there is one solid ground plane with no

noisy currents around the chip. All voltage levels are measured with respect to this pin.

EPAD at ground potential. EPAD is connected to SGND internally. However, it is highly

recommended to solder it directly to the ground plane for better thermal performance and noise

immunity.

Pin #

(QFN)

Pin #

(HTSSOP)

Name

Function

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