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MPC602EC/D Datasheet(PDF) 12 Page - NXP Semiconductors |
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MPC602EC/D Datasheet(HTML) 12 Page - NXP Semiconductors |
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12 / 26 page ![]() 12 PowerPC 602 RISC Microprocessor Hardware Specifications Figure 4. Output Timing Diagram 1.3.3 JTAG AC Timing Specifications Table 9 provides the JTAG AC timing specifications. Table 9. JTAG AC Timing Specifications (Independent of SYSCLK) Vdd = 3.3 ± 10% V dc, GND = 0 V dc, CL = 50 pF, 0 ≤ TJ ≤ 105 °C Num Characteristic Min Max Unit Notes TCK frequency of operation 0 16 MHz 1 TCK cycle time 62.5 — ns 2 TCK clock pulse width measured at 1.4 V 25 — ns 3 TCK rise and fall times 0 3 ns 4 TRST setup time to TCK rising edge 13 — ns 1 5 TRST assert time 40 — ns 6 Boundary-scan input data setup time 6 — ns 2 7 Boundary-scan input data hold time 27 — ns 2 8 TCK to output data valid 4 25 ns 3 SYSCLK 13 15 TS, BB, BR, VM VM VM = Midpoint Voltage (1.4 V) 14 VM ARTRY 12 13 14 15 AD0–AD63 RESETO, QREQ, CKSTP_OUT TDO 16 13 17 18 12 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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