5

Figure 4. Transmitter Latency.

Figure 3. Transmitter Section Timing.

HDMP-1637A (Transmitter Section)

Timing Characteristics

Symbol

Parameter

Units

Min.

Typ.

Max.

Setup Time

nsec

1.5

Hold Time

nsec

1.0

Transmitter Latency

nsec

3.5

bits

4.4

Note:

1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered

by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by

the rising edge of the first bit transmitted).

DATA

DATA

TX[9]-TX[0]

tSETUP

tHOLD

REFCLK

DATA

DATA

DATA

0.0 V AC

2.0 V

0.8 V

DATA BYTE B

DATA BYTE C

TX[0]-TX[9]

DATA BYTE A

± DOUT

0.0 V AC

DATA BYTE B

t_TXLAT

T5

T6

T7

T8

T9

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T0

T1

T2

T3

T4

T5

REFCLK