MPC8560CPXAPDB datasheet(11/108 Pages) FREESCALE

11 / 108 page

MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Electrical Characteristics

Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8560.

Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD

The MPC8560 core voltage must always be provided at nominal 1.2 V (see Table 2 for actual recommended core

voltage). Voltage to the processor interface I/Os are provided through separate sets of supply pins and must be

provided at the voltages shown in Table 2. The input voltage threshold scales with respect to the associated I/O

supply voltage. OVDD and LVDD based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS

type specifications. The DDR SDRAM interface uses a single-ended differential receiver referenced the externally

supplied MVREF signal (nominally set to GVDD/2) as is appropriate for the SSTL2 electrical signaling standard.

Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8560 for the 3.3-V signals,

respectively.

Figure 3. Maximum AC Waveforms on PCI interface for 3.3-V Signaling

GND

GND – 0.3 V

GND – 0.7 V

Not to Exceed 10%

G/L/OVDD + 20%

G/L/OVDD

G/L/OVDD + 5%

of tSYS

1. Note that tSYS refers to the clock period associated with the SYSCLK signal.

VIH

VIL

Note:

Undervoltage

Waveform

Overvoltage

Waveform

11 ns

(Min)

+7.1 V

7.1 V p-to-p

(Min)

4 ns

(Max)

–3.5 V

7.1 V p-to-p

(Min)

62.5 ns

+3.6 V

0 V

4 ns

(Max)

MPC8560CPXAPDB Datasheet(PDF) 11 Page - Freescale Semiconductor, Inc

MPC8560CPXAPDB Datasheet(HTML) 11 Page - Freescale Semiconductor, Inc

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