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UPD75P4308GS Datasheet(PDF) 30 Page - Renesas Technology Corp |
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UPD75P4308GS Datasheet(HTML) 30 Page - Renesas Technology Corp |
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30 / 61 page ![]() µPD75P4308 28 Data Sheet U10909EJ2V1DS 8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY The program memory in the µPD75P4308 is a 8192 × 8-bit electrically write-enabled one-time PROM. The pins listed in the table below are used for this one-time PROM’s write/verify operations. Clock input from the X1 pin is used instead of address input as a method for updating addresses. Pin name Function VPP Pin (usually VDD) where programming voltage is applied during program memory write/verify X1, X2 Clock input pin for address updating during program memory write/ verify. Input the X1 pin’s inverted signal to the X2 pin. MD0-MD3 Operation mode selection pin for program memory write/verify D0/P60/KR0-D3/P63/KR3 (lower 4) 8-bit data I/O pin for program memory write/verify D4/P50-D7/P53 (upper 4) VDD Pin where power supply voltage is applied. Power voltage range for normal operation is 1.8 to 5.5 V. Apply 6.0 V for program memory write/verify. Caution Pins not used for program memory write/verify connect to Vss via a pull-down resistor. 8.1 Operation Modes for Program Memory Write/Verify When +6 V is applied to the µPD75P4308’s VDD pin and +12.5 V is applied to its VPP pin, program write/verify modes are in effect. Furthermore, the following detailed operation modes can be specified by setting pins MD0 to MD3 as shown below. Operation mode specification Operation mode VPP VDD MD0 MD1 MD2 MD3 +12.5 V +6 V H L H L Zero-clear program memory address LH HH Write mode LL HH Verify mode H × HH Program inhibit mode × : L or H |
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