ES9842PRO datasheet(68/167 Pages) ESS

68 / 167 page

CONFIDENTIAL ADVANCE INFORMATION

ES9842 PRO Product Datasheet

VERSION 0.5

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

Bits

[7]

[6:4]

[3]

[2]

[1]

[0]

Default

1'b0

3'd0

1'b0

Bits

Mnemonic

Description

[7]

FORCE_PHASE_CLK_IADC

Sets phase of CLK_IADC by PHASE_CLK_IADC.

• 1'b0: Auto phase tuning if AUTO_CLK_IADC_PHASE_SYNC

is set (default)

• 1'b1: Sets phase by PHASE_CLK_IADC

[6:4]

PHASE_CLK_IADC

Sets phase of CLK_IADC relative to SYS_CLK when

FORCE_PHASE_CLK_IADC is set. For 48M SYS_CLK and 24M

CLK_IADC only.

• 3'd0: Phase 0 (default)

• 3'd1: Phase 1

• others: Reserved

[3]

INVERT_SAMPLE_CLOCK_CH4

Inverts ADC Ch4 data sampling clock.

• 1'b0: Not inverted (default)

• 1'b1: Inverted

[2]

INVERT_SAMPLE_CLOCK_CH3

Inverts ADC Ch3 data sampling clock.

• 1'b0: Not inverted (default)

• 1'b1: Inverted

[1]

INVERT_SAMPLE_CLOCK_CH2

Inverts ADC Ch2 data sampling clock.

• 1'b0: Not inverted (default)

• 1'b1: Inverted

[0]

INVERT_SAMPLE_CLOCK_CH1

Inverts ADC Ch1 data sampling clock.

• 1'b0: Not inverted (default)

• 1'b1: Inverted

ES9842PRO Datasheet(PDF) 68 Page - ESS Technology,Inc

ES9842PRO Datasheet(HTML) 68 Page - ESS Technology,Inc

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