STMPE811 datasheet(15/66 Pages) STMICROELECTRONICS

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STMPE811

SPI interface

Doc ID 14489 Rev 5

15/66

SPI interface

The SPI (serial peripheral interface) in STMPE811 uses a 4-wire communication connection

(DATA IN, DATA OUT, CLK, CS). In the diagram, “Data in” is referred to as MOSI (master

out slave in) and “DATA out” is referred to as MISO (master in slave out).

5.1

SPI protocol definition

The SPI follows a byte-sized transfer protocol. All transfers begin with an assertion of CS_n

signal (falling edge). The protocol for reading and writing is different and the selection

between a read and a write cycle is dependent on the first captured bit on the slave device.

A '1' denotes a read operation and a '0' denotes a write operation. The SPI protocol defined

in this section is shown in Figure 3.

The following are the main features supported by this SPI implementation.

●

Support of 1 MHz maximum clock frequency.

●

Support for autoincrement of address for both read and write.

●

Full duplex support for read operation.

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Daisy chain configuration support for write operation.

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Robust implementation that can filter glitches of up to 50 ns on the CS_n and SCL pins.

●

Support for all 4 modes of SPI as defined by the CPHA, CPOL bits on SPICON.

5.1.1

The following steps need to be followed for the register read through the SPI.

Assert CS_n by driving a '0' on this pin.

Drive a '1' on the first SCL launch clock on MOSI to select a read operation.

The next 7 bits on MOSI denote the 7-bit register address (MSB first).

The next address byte can now be transmitted on the MOSI. If the autoincrement bit is

set, the following address transmitted on the MOSI is ignored. Internally, the address is

incremented. If the autoincrement bit is not set, then the following byte denotes the

address of the register to be read next.

Read data is transmitted by the slave device on the MISO (MSB first), starting from the

launch clock following the last address bit on the MOSI.

Full duplex read operation is achieved by transmitting the next address on MOSI while

the data from the previous address is available on MISO.

To end the read operation, a dummy address of all 0's is sent on MOSI.

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