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WM8766 Datasheet(PDF) 9 Page - Wolfson Microelectronics plc |
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WM8766 Datasheet(HTML) 9 Page - Wolfson Microelectronics plc |
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9 / 36 page  Production Data WM8766 w PD Rev 4.1 July 2005 9 DIGITAL AUDIO INTERFACE – SLAVE MODE BCLK DIN1/2/3 LRCLK WM8766 DAC DSP/ DECODER 3 Figure 4 Audio Interface – Slave Mode BCLK LRCLK t BCH t BCL t BCY DIN1/2/3 t LRSU t DS t LRH Figure 5 Digital Audio Data Timing – Slave Mode Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns LRCLK set-up time to BCLK rising edge tLRSU 10 ns LRCLK hold time from BCLK rising edge tLRH 10 ns DIN1/2/3 set-up time to BCLK rising edge tDS 10 ns DIN1/2/3 hold time from BCLK rising edge tDH 10 ns Table 3 Digital Audio Data Timing – Slave Mode |
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