CC1110-RTR1 datasheet(97/203 Pages) TI

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CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 97 of 202

TIMIF.OVFIM. If there are other pending

interrupts, the corresponding interrupt flag

must be cleared by software before a new

interrupt request is generated. Also, enabling

an interrupt mask bit will generate a new

interrupt request if the corresponding interrupt

flag is set.

13.3.10 Timer 1 DMA Triggers

There are three DMA triggers associated with

Timer 1. These are DMA triggers T1_CH0,

T1_CH1 and T1_CH2 which are generated on

timer compare events as follows:

•

T1_CH0 – channel 0 compare

•

T1_CH1 – channel 1 compare

•

T1_CH2 – channel 2 compare

See Table 37 for a list of all DMA triggers.

13.3.11 Timer 1 Registers

This section describes the Timer 1 registers

that consist of the following registers:

•

T1CNTH – Timer 1 Count High

•

T1CNTL – Timer 1 Count Low

•

T1CTL – Timer 1 Control and Status

•

T1CCTLx

–

Timer

Channel

Capture/Compare Control

•

T1CCxH

–

Timer

Channel

Capture/Compare Value High

•

T1CCxL

–

Timer

Channel

Capture/Compare Value Low

CC1110-RTR1 Datasheet(PDF) 97 Page - Texas Instruments

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