DG401_06 datasheet(6/12 Pages) INTERSIL

6 / 12 page

FN3284.11

November 20, 2006

Application Information

Dual Slope Integrators

The DG403 is well suited to configure a selectable slope

integrator. One control signal selects the timing capacitor C1

or C2. Another one selects eIN or discharges the capacitor in

preparation for the next integration cycle.

Peak Detector

A3 acting as a comparator provides the logic drive for

operating SW1. The output of A2 is fed back to A3 and

compared to the analog input eIN. If eIN > eOUT the output of

A3 is high keeping SW1 closed. This allows C1 to charge up

to the analog input voltage. When eIN goes below eOUT, A3

goes negative, turning SW1 off. The system will therefore

store the most positive analog input experienced.

FIGURE 6. CROSSTALK TEST CIRCUIT

FIGURE 7. CAPACITANCES TEST CIRCUIT

Test Circuits and Waveforms (Continued)

0V, 2.4V

ANALYZER

+15V

V+

VS1

SIGNAL

GENERATOR

GND

IN1

VD1

IN2

0V, 2.4V

V-

-15V

VD2

+5V

VS2

+15V

V+

GND

INX

V-

-15V

IMPEDANCE

ANALYZER

0V, 2.4V

+5V

AS REQUIRED

V-

GND

-15V

IN2

IN1

+15V

+5V

V+

DG403

eOUT

eIN

INTEGRATE/

SCOPE

TTL

RESET

SELECT

FIGURE 8. DUAL SLOPE INTEGRATOR

eOUT

eIN

SW2

SW1

RESET

DG401

FIGURE 9. POSITIVE PEAK DETECTOR

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