NXP Semiconductors

PCF85063A

Tiny Real-Time Clock/calendar with alarm function and I2C-bus

VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +85 °C; fosc = 32.768 kHz; quartz Rs = 60 kΩ; CL = 7 pF; unless otherwise

specified. All timing values are valid within the operating supply voltage and temperature range and referenced to VIL and

VIH with an input voltage swing of VSS to VDD[1].

Symbol

Parameter

Conditions

Min

Max

Unit

tHD;STA

hold time (repeated)

START condition

0.6

-

μs

tSU;STA

set-up time for a

repeated START

condition

0.6

-

μs

tLOW

LOW period of the

SCL clock

1.3

-

μs

tHIGH

HIGH period of the

SCL clock

0.6

-

μs

tr

rise time of both SDA

and SCL signals

20

300

ns

tf

fall time of both SDA

and SCL signals

[3][4] 20 × (VDD / 5.5 V) 300

ns

tBUF

bus free time between

a STOP and START

condition

1.3

-

μs

tSU;DAT

data set-up time

100

-

ns

tHD;DAT

data hold time

0

-

ns

tSU;STO

set-up time for STOP

condition

0.6

-

μs

tVD;DAT

data valid time

0

0.9

μs

tVD;ACK

data valid

acknowledge time

0

0.9

μs

tSP

pulse width of

spikes that must be

suppressed by the

input filter

0

50

ns

Table 41. I2C-bus characteristics...continued

[1]

A detailed description of the I2C-bus specification is given in [8].

[2]

I2C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.

[3]

A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined

region of the falling edge of SCL.

[4]

The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This

allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum

specified tf.

PCF85063A

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Product data sheet

Rev. 7.1 — 8 November 2023

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