PCF85063ATTSLASHAJ datasheet(6/55 Pages) NXP

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NXP Semiconductors

PCF85063A

Tiny Real-Time Clock/calendar with alarm function and I2C-bus

Bit

Symbol

Value

Description

Reference

RTC clock is stopped; all RTC divider chain

flip-flops are asynchronously set logic 0

software reset

0[1]

no software reset

initiate software reset[2]; this bit always

returns a 0 when read

Section 7.2.1.3

unused

correction interrupt enable

0[1]

no correction interrupt generated

CIE

interrupt pulses are generated at every

correction cycle

Section 7.2.3

12 or 24-hour mode

0[1]

24-hour mode is selected

12_24

12-hour mode is selected

Section 7.3.3

Section 7.5.3

internal oscillator capacitor selection for

quartz crystals with a corresponding load

capacitance

0[1]

7 pF

CAP_SEL

12.5 pF

Table 5. Control_1 - control and status register 1 (address 00h) bit description...continued

[1]

Default value.

[2]

For a software reset, 0101 1000 (58h) must be sent to register Control_1 (see Section 7.2.1.3).

7.2.1.1 EXT_TEST: external clock test mode

A test mode is available which allows for on-board testing. In this mode, it is possible to set up test conditions

and control the operation of the RTC.

The test mode is entered by setting bit EXT_TEST in register Control_1. Then pin CLKOUT becomes an input.

The test mode replaces the internal clock signal with the signal applied to pin CLKOUT.

The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a maximum period of 1

000 ns. The internal clock, now sourced from CLKOUT, is divided down to 1 Hz by a 26 divide chain called a

prescaler. The prescaler can be set into a known state by using bit STOP. When bit STOP is set, the prescaler

is reset to 0. (STOP must be cleared before the prescaler can operate again.)

From a stop condition, the first 1 second increment will take place after 32 positive edges on pin CLKOUT.

Thereafter, every 64 positive edges cause a 1 second increment.

Remark: Entry into test mode is not synchronized to the internal 64 Hz clock. When entering the test mode, no

assumption as to the state of the prescaler can be made.

Operation example:

1. Set EXT_TEST test mode (register Control_1, bit EXT_TEST = 1).

2. Set STOP (register Control_1, bit STOP = 1).

3. Clear STOP (register Control_1, bit STOP = 0).

4. Set time registers to desired value.

5. Apply 32 clock pulses to pin CLKOUT.

PCF85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7.1 — 8 November 2023

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