AD9957SLASHPCBZ datasheet(31/60 Pages) AD

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AD9957

Rev. 0 | Page 31 of 60

START ADDRESS

RAM

ADDRESS

END ADDRESS

1 PDCLK CYCLE

M DDS CLOCK CYCLES

I/O_UPDATE OR

RT TRANSITION

Figure 45. Continuous Bidirectional Ramp Timing Diagram

RAM Continuous Bidirectional Ramp Mode

In continuous bidirectional ramp mode, upon assertion of an

I/O update or a state change on the RT pin, the RAM begins

playback operation using the parameters programmed into the

selected RAM segment register. Data is extracted from RAM

over the specified address range contained in the start address

and end address. The data is delivered at the appropriate rate

and to the destination as specified by the RAM playback

destination bit.

The playback rate is governed by the timer internal to the RAM

state machine and its period ( t) is determined by the state of

the RAM playback destination bit as detailed in the RAM

Playback Operation section.

After initialization, the internal state machine begins extracting

data from the RAM at the start address of the active RAM

segment register and increments the address counter until it

reaches the end address, at which point the state machine

reverses the direction of the address counter and begins

decrementing through the address range. Whenever one of the

terminal addresses is reached, the state machine reverses the

address counter; the process continues indefinitely.

Note that a change in state of the RT pin aborts the current

waveform and the newly selected RAM segment register is used

to initiate a new waveform.

A graphic representation of the continuous bidirectional ramp

mode is shown in Figure 45. The circled numbers in Figure 45

indicate specific events, explained as follows:

Event 1—an I/O update or state change on the RT pin has

activated the RAM continuous bidirectional ramp mode. The

state machine initializes to the start address of the active RAM

segment register. The state machine begins incrementing

through the specified address range.

Event 2—the state machine reaches the end address of the active

RAM segment register.

Event 3—the state machine reaches the start address of the

active RAM segment register.

This action continues indefinitely until the next I/O update or

state change on the RT pin.

AD9957/PCBZ Datasheet(PDF) 31 Page - Analog Devices

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