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PLS159 Datasheet(PDF) 6 Page - NXP Semiconductors

Part # PLS159
Description  Programmable logic sequencer 16 횞 45 횞 12
PDF  12 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

PLS159 Datasheet(HTML) 6 Page - NXP Semiconductors

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Philips Semiconductors Programmable Logic Devices
Product specification
PLS159A
Programmable logic sequencer
(16
× 45 × 12)
October 22, 1993
30
AC ELECTRICAL CHARACTERISTICS
0
°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V, R1 =470Ω, R2 = 1kΩ
LIMITS
SYMBOL
PARAMETER
FROM
TO
TEST CONDITION
MIN
TYP1
MAX
UNIT
Pulse width
tCKH
Clock2 High
CK +
CK –
CL = 30pF
20
15
ns
tCKL
Clock Low
CK –
CK +
CL = 30pF
20
15
ns
tCKP
Period
CK +
CK +
CL = 30pF
55
45
ns
tPRH
Preset/Reset pulse
(I,B) –
(I,B) +
CL = 30pF
35
30
ns
Setup time5
tIS1
Input
(I,B)
±
CK +
CL = 30pF
35
30
ns
tIS2
Input (through Fn)
F
±
CK +
CL = 30pF
15
10
ns
tIS3
Input (through
Complement Array)4
(I,B)
±
CK +
CL = 30pF
55
45
ns
Hold time
tIH1
Input
(I,B)
±
CK +
CL = 30pF
0
–5
ns
tIH2
Input (through Fn)
F
±
CK +
CL = 30pF
15
10
ns
Propagation delay
tCKO
Clock
CK +
F
±
CL = 30pF
15
20
ns
tOE1
Output enable3
OE –
F –
CL = 30pF
20
30
ns
tOD1
Output disable3
OE +
F +
CL = 5pF
20
30
ns
tPD
Output
(I,B)
±
B
±
CL = 30pF
25
35
ns
tOE2
Output enable3
(I,B) +
B
±
CL = 30pF
20
30
ns
tOD2
Output disable3
(I,B) –
B +
CL = 5pF
20
30
ns
tPRO
Preset/Reset
(I,B) +
F
±
CL = 30pF
35
45
ns
tPPR
Power-on/preset
VCC +
F –
CL = 30pF
0
10
ns
NOTES:
1. All typical values are at VCC = 5V, Tamb = +25°C.
2. To prevent spurious clocking, clock rise time (10% – 90%)
≤ 10ns.
3. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output
voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed.
4. When using the Complement Array tCKP = 75ns (min).
5. Limits are guaranteed with 12 product terms maximum connected to each sum term line.
VOLTAGE WAVEFORMS
MEASUREMENTS:
All circuit delays are measured at the +1.5V level
of inputs and outputs, unless otherwise specified.
90%
10%
5ns
5ns
5ns
5ns
90%
10%
+3.0V
+3.0V
0V
0V
tR
tF
Input Pulses
TEST LOAD CIRCUIT
+5V
CL
R1
R2
S1
GND
BZ
BY
INPUTS
I0
In
BW
BX
OUTPUTS
C2
C1
DUT
NOTE:
C1 and C2 are to bypass VCC to GND.
VCC
OE
CLK



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