PLS159 datasheet(3/12 Pages) PHILIPS

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Philips Semiconductors Programmable Logic Devices

Product specification

PLS159A

Programmable logic sequencer

(16

× 45 × 12)

October 22, 1993

FUNCTIONAL DIAGRAM

(LOGIC TERMS)

(CONTROL TERMS)

T31

(4)

RB PA

CLK

LOGIC FUNCTION

STATE REGISTER

Sn + 1

PRESENT STATE

⋅ B ⋅ C ⋅ . . .

NEXT STATE

SET Q0: J0 = (Q3 ⋅ Q2 ⋅ Q1 ⋅ Q0) ⋅ A ⋅ B ⋅ C . . .

K0 = 0

RESET Q1: J1 = 0

K1 = (Q3⋅ Q2 ⋅ Q1 ⋅ Q0) ⋅ A ⋅ B ⋅ C . . .

HOLD Q2: J2 = 0

K2 = 0

TOGGLE Q3: J3 = (Q3 ⋅ Q2 ⋅ Q1 ⋅ Q0) ⋅ A ⋅ B ⋅ C . . .

K3 = (Q3⋅ Q2 ⋅ Q1 ⋅ Q0) ⋅ A ⋅ B ⋅ C . . .

NOTE:

Similar logic functions are applicable for D

and T mode flip-flops.

FLIP-FLOP TRUTH TABLE

K Q

Hi-Z

X H

H X

↑

H Q

↑

+10V

↑

H* *

↑

X H

L* *

NOTES:

1. Positive Logic:

J-K = T0 + T1 + T2 ……………… T31

Tn = C⋅ (I0 ⋅ I1 ⋅ I2 …) ⋅ (Q0 ⋅ Q1 …) ⋅

(B0

⋅ B1 ⋅ …)

↑ denotes transition from Low to High level.

3. X = Don’t care

4. * = Forced at Fn pin for loading the J-K

flip-flop in the Input mode. The load

control term, Ln must be enabled (HIGH)

and the p-terms that are connected to the

associated flip-flop must be forced LOW

(disabled) during Preload.

5. At P = R = H, Q = H. The final state of Q

depends on which is released first.

6. * * = Forced at Fn pin to load J-K flip-flop

independent of program code (Diagnostic

mode), 3-State B outputs.

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