Directly shorting the output to the opposite supply rail (V+ when output "low" or V- when output "High") can result

in thermal runaway and eventual device destruction at high (>12V) supply voltages. If output shorts are possible,

a series current limiting resistor is recommended to limit the power dissipation.

Unused push-pull outputs mustbe left floating, and never tied to a supply, ground, or another output.

5.4.2.2 TLV1822-EP Open-Drain Output

The TLV1822-EP features an open-drain (also commonly called open collector) sinking-only output stage

enabling the output logic levels to be pulled up to an external voltage from 0V up to 40V, independent of

the comparator supply voltage (V+). The open-drain output allows logical OR'ing of multiple open drain outputs

and logic level translation. TI recommends setting the pull-up resistor current to between 100uA and 1mA. Lower

value pull-up resistor values will help increase the rising edge rise-time, but at the expense of increasing VOL and

higher power dissipation. The rise-time is dependent on the time constant of the total pull-up resistance and total

load capacitance. Large value pull-up resistors (>1MΩ) will create an exponential rising edge due to the output

RC time constant and increase the rise-time.

Directly shorting the output to V+ can result in thermal runaway and eventual device destruction at high (>12V)

pull-up voltages. If output shorts are possible, a series current limiting resistor is recommended to limit the power

dissipation.

Unused open drain outputs may be left floating, or may be tied to the V- pin if floating pins are not desired.

5.4.3 Power-On Reset (POR)

The TLV18x2-EP family has an internal Power-on-Reset (POR) circuit for known start-up or power-down

conditions. While the power supply (V+) is ramping up or ramping down, the POR circuitry will be activated

for up to 200µs after the minimum supply voltage threshold of 2.4V is crossed, or immediately when the supply

voltage drops below 2.4V. When the supply voltage is equal to or greater than the minimum supply voltage, and

after the delay period, the comparator output reflects the state of the differential input (VID).

For the TLV1812-EP push-pull output devices, the output is held low during the POR period (ton).

For the TLV1822-EP open drain output option the POR circuit will keep the output high impedance (Hi-Z) during

the POR period (ton).

tON

VOH/2

V-

OUT

V+

(V-) + 2.4V

V-

Figure 5-3. Power-On Reset Timing Diagram

Note: The output voltage rises with the pull-up voltage during the POR period.

5.4.4 Hysteresis

The TLV18x2-EP family does not have internal hysteresis. Due to the wide effective bandwidth and low input

offset voltage, it is possible for the output to "chatter" when the absolute differential voltage is near zero as the

comparator triggers on it's own internal wideband noise. This is normal comparator behavior and is expected. TI

recommends that the user add external hysteresis if slow moving signals are expected. See Section 6.1.2 in the

following section.

www.ti.com

TLV1812-EP, TLV1822-EP

SNOSDJ3 – MAY 2024

Copyright © 2024 Texas Instruments Incorporated

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