MPC5200B datasheet(46/78 Pages) FREESCALE

46 / 78 page

MPC5200B Data Sheet, Rev. 1

Electrical and Thermal Characteristics

Freescale Semiconductor

NOTE

Output timing is specified at a nominal 50 pF load.

Figure 33. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0)

Table 37. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0)

Sym

Description

Min

Max

Units

SpecID

Cycle time

1024

IP-Bus Cycle(1)

NOTES:

Inter Peripheral Clock is defined in the MPC5200B User Manual [1].

A11.12

Clock high or low time

512

IP-Bus Cycle(1)

A11.13

Slave select to clock delay

15.0

—

A11.14

Output Data valid after Slave Select (SS)

—

50.0

A11.15

Output Data valid after SCK

—

50.0

A11.16

Input Data setup time

50.0

—

A11.17

Input Data hold time

0.0

—

A11.18

Slave disable lag time

15.0

—

A11.19

Sequential Transfer delay

—

IP-Bus Cycle(1)

A11.20

SCK

(CLKPOL=0)

SCK

(CLKPOL=1)

MOSI

Input

MISO

Output

MPC5200B Datasheet(PDF) 46 Page - Freescale Semiconductor, Inc

MPC5200B Datasheet(HTML) 46 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

Datasheet Download

Link URL