MPC5200B datasheet(13/78 Pages) FREESCALE

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Electrical and Thermal Characteristics

MPC5200B Data Sheet, Rev. 1

Freescale Semiconductor

The MPC5200B clock generation uses two phase locked loop (PLL) blocks.

•

The system PLL (SYS_PLL) takes an external reference frequency and generates the internal

system clock. The system clock frequency is determined by the external reference frequency and

the settings of the SYS_PLL configuration.

•

The e300 core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry. The e300

core clock frequency is determined by the system clock frequency and the settings of the

CORE_PLL configuration.

3.2.1

System Oscillator Electrical Characteristics

3.2.2

RTC Oscillator Electrical Characteristics

3.2.3

System PLL Electrical Characteristics

Table 8. System Oscillator Electrical Characteristics

Characteristic

Sym

Notes

Min

Typical

Max

Unit

SpecID

SYS_XTAL frequency

fsys_xtal

15.6

33.3

35.0

MHz

O1.1

Oscillator start-up time

tup_osc

—

O1.2

Table 9. RTC Oscillator Electrical Characteristics

Characteristic

Sym

Notes

Min

Typical

Max

Unit

SpecID

RTC_XTAL frequency

frtc_xtal

—

32.768

—

kHz

O2.1

Table 10. System PLL Specifications

Characteristic

Sym

Notes

Min

Typical

Max

Unit

SpecID

SYS_XTAL frequency

fsys_xtal

(1)

NOTES:

The SYS_XTAL frequency and PLL Configuration bits must be chosen such that the resulting system frequency,

CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating

frequencies.

15.6

33.3

35.0

MHz

O3.1

SYS_XTAL cycle time

tsys_xtal

(1)

66.6

30.0

28.5

O3.2

SYS_XTAL clock input jitter

tjitter

(2)

This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different

types of jitter can exist on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is

rejected. Systemic jitter will be passed into and through the PLL to the internal clock circuitry.

—

150

O3.3

System VCO frequency

fVCOsys

(1)

250

533

800

MHz

O3.4

System PLL relock time

tlock

(3)

Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required

for the PLL lock after a stable VDD and CORE_SYSCLKare reached during the power-on reset sequence. This

specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.

—

100

µsO3.5

MPC5200B Datasheet(PDF) 13 Page - Freescale Semiconductor, Inc

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