LTC2414IGN datasheet(10/48 Pages) LINER

10 / 48 page

LTC2414/LTC2418

241418fa

CH0 to CH15 (Pin 21 to Pin 28 and Pin 1 to Pin 8): Analog

Inputs. May be programmed for single-ended or differen-

tial mode. CH8 to CH15 (Pin 1 to Pin 8) not connected on

the LTC2414.

VCC (Pin 9): Positive Supply Voltage. Bypass to GND

(Pin 15) with a 10

µF tantalum capacitor in parallel with

0.1

µF ceramic capacitor as close to the part as possible.

COM (Pin 10): The common negative input (IN–) for all

single-ended multiplexer configurations. The voltage on

Channel 0 to 15 and COM input pins can have any value

between GND – 0.3V and VCC + 0.3V. Within these limits,

the two selected inputs (IN+ and IN–) provide a bipolar

input range (VIN = IN+ – IN–) from – 0.5 • VREF to 0.5 • VREF.

Outside this input range, the converter produces unique

overrange and underrange output codes.

REF+ (Pin 11), REF– (Pin 12): Differential Reference

Input. The voltage on these pins can have any value

between GND and VCC as long as the positive reference

input, REF+, is maintained more positive than the negative

reference input, REF –, by at least 0.1V.

GND (Pin 15): Ground. Connect this pin to a ground plane

through a low impedance connection.

CS (Pin 16): Active LOW Digital Input. A LOW on this pin

enables the SDO digital output and wakes up the ADC.

Following each conversion the ADC automatically enters

the Sleep mode and remains in this low power state as

long as CS is HIGH. A LOW-to-HIGH transition on CS

during the Data Output transfer aborts the data transfer

and starts a new conversion.

SDO (Pin 17): Three-State Digital Output. During the Data

Output period, this pin is used as the serial data output.

When the chip select CS is HIGH (CS = VCC), the SDO pin

is in a high impedance state. During the Conversion and

Sleep periods, this pin is used as the conversion status

output. The conversion status can be observed by pulling

CS LOW.

SCK (Pin 18): Bidirectional Digital Clock Pin. In Internal

Serial Clock Operation mode, SCK is used as the digital

output for the internal serial interface clock during the Data

Output period. In External Serial Clock Operation mode,

SCK is used as the digital input for the external serial

interface clock during the Data Output period. A weak

internal pull-up is automatically activated in Internal Serial

Clock Operation mode. The Serial Clock Operation mode is

determined by the logic level applied to the SCK pin at

power up or during the most recent falling edge of CS.

FO (Pin 19): Frequency Control Pin. Digital input that

controls the ADC’s notch frequencies and conversion

time. When the FO pin is connected to VCC (FO = VCC), the

converter uses its internal oscillator and the digital filter

first null is located at 50Hz. When the FO pin is connected

to GND (FO = 0V), the converter uses its internal oscillator

and the digital filter first null is located at 60Hz. When FO

is driven by an external clock signal with a frequency fEOSC,

the converters use this signal as their system clock and the

digital filter first null is located at a frequency fEOSC/2560.

SDI (Pin 20): Serial Digital Data Input. During the Data

Output period, this pin is used to shift in the multiplexer

address started from the first rising SCK edge. During the

Conversion and Sleep periods, this pin is in the DON’T

CARE state. However, a HIGH or LOW logic level should be

maintained on SDI in the DON’T CARE mode to avoid an

excessive current in the SDI input buffers.

NC Pins: Do Not Connect.

PI FU CTIO S

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