3.3V, 8-Bit, Programmable Timing Element

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9

effect on power-up. The most flexibility when using par-

allel mode occurs when the delay is being controlled

by a microprocessor.

There are two common parallel interface implementa-

tions used to control the DS1123L using a microproces-

sor (see Figure 2). LE can be used to latch the data

from the microprocessor, which allows the data bus to

be shared with other peripherals, or LE can be tied

high, which causes the DS1123L to adjust its delay

immediately following a change to the parallel inputs.

required after an adjustment is made before the input

signal is accurately delayed according to the new set-

ting. Figures 3 and 4 show the timing required for these

implementations.

Using the Serial Programming Interface

The 3-wire serial interface is enabled by connecting P/S

When LE is set at a high logic level, it enables the reg-

ister and CLK clocks the data, D, into the register one

bit at a time starting with the most significant bit. After

all 8 bits are shifted into the DS1123L, LE is pulled low

to end the data transfer and activate the new value. A

before the signal delay meets its specified accuracy. A

timing diagram for the serial interface is shown in

Figure 6. The 3-wire interface also has an output (Q)

that can be used to cascade multiple 3-wire devices,

and it can be used to read the current value of the

devices on the bus.

LE

P0-P7

P/S

8

MICROPROCESSOR

ADDITIONAL

PERIPHERAL

ADDITIONAL

PERIPHERAL

A) SHARING THE PARALLEL INTERFACE

WITH ADDITIONAL PERIPHERALS

MICROPROCESSOR

8

B) A PARALLEL INTERFACE DEDICATED

TO A DS1123L

DS1123L

LE

P0-P7

P/S

DS1123L

Figure 2. Parallel Interface Options for DS1123L

PREVIOUS VALUE

PARALLEL

INPUTS

P0–P7

DELAY

TIME

NEW VALUE

NEW VALUE

PREVIOUS VALUE

Figure 3. Nonlatched Parallel Timing Diagram

ENABLE

(LE)

PREVIOUS VALUE

NEW VALUE

NEW VALUE

PARALLEL

INPUTS

PO–P7

DELAY

TIME

Figure 4. Latched Parallel Timing Diagram