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ICS952906AFLFT Datasheet(PDF) 10 Page - Integrated Circuit Systems |
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ICS952906AFLFT Datasheet(HTML) 10 Page - Integrated Circuit Systems |
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10 / 23 page  10 Integrated Circuit Systems, Inc. ICS952906A 1236A—08/06/07 Table 5: Asynchronous 3V66/PCI Frequency Table Byte6 Bit7 Byte3 Bit7 3V66/PCI Frequency 0 0 66.66/33.33 0 1 80.00/40.00 1 0 72.73/36.36 I 2C Table: Output Control Register Control Function Bit 7 48MHz_0 2x output drive 0=2x drive RW 1 Bit 6 PCI ADIV PCI Async Divider Cntr RW 0 Bit 5 Reserved Reserved RW 1 Bit 4 3V66_0 Output Control RW 1 Bit 3 Reserved Reserved RW 1 Bit 2 PCICLK_F2 Output Control RW 1 Bit 1 PCICLK_F1 Output Control RW 1 Bit 0 PCICLK_F0 Output Control RW 1 I 2C Table: Reserved Register Control Function Bit 7 Reserved Reserved RW 0 Bit 6 Mode Sel1 RW 0 Bit 5 Mode Sel0 RW 0 Bit 4 3V66_2 Output Control RW 1 Bit 3 M PLL2 Div3 RW X Bit 2 M PLL2 Div2 RW X Bit 1 M PLL2 Div1 RW X Bit 0 M PLL2 Div0 RW X -- See Table 4: Mode Selection Table Disable Enable Disable Enable Disable Enable -- Disable Enable AGP/2 PLL3 Freq/24 Disable Enable -- The decimal representation of M PLL2 Div (3:0) + 2 is equal to REF divider value for PLL2 01 01 - - - - PWD 7 Byte 5 Pin # Name Type PWD - 2x drive normal Name Type Byte 4 Pin # PLL Mode Selection Bits M Divider Programming bits for Async mode 2&3 - 25 - - - 29 - 9 8 - Table 4: Mode Selection Table Mode Standard Overclock Mode(I) CPU Overclock Mode(II) Graphic Overclock Mode(III) IIC Control Byte 5 bit(6:5) = 00 Byte 5 bit(6:5) = 01 Byte 5 bit(6:5) = 10 25MHz From? PLL3 PLL3 PLL1 3V66/PCI From? PLL1 (Needed to be align w/ CPU) PLL3 PLL3 Spreading CPU/3V66/PCI have spread Only CPU clocks have spread. Only CPU clocks have spread. I 2C Table: Vendor & Revision ID Register Control Function Bit 7 ASEL0 3V66/PCI Freq Select RW 0 Bit 6 N PLL2 Div6 RW X Bit 5 N PLL2 Div5 RW X Bit 4 N PLL2 Div4 RW X Bit 3 N PLL2 Div3 RW X Bit 2 N PLL2 Div2 RW X Bit 1 N PLL2 Div1 RW X Bit 0 N PLL2 Div0 RW X The decimal representation of N PLL2 Div (6:0) + 8 is equal to VCO divider value for PLL2. Byte 6 Pin # Name - - - PWD - - N Divider Programming bits for Async mode 2&3 - - - See Table 5: Async AGP/PCI Freq Table 01 Type |
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