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PPC440GP-3CC466C Datasheet(PDF) 78 Page - Applied Micro Circuits Corporation |
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PPC440GP-3CC466C Datasheet(HTML) 78 Page - Applied Micro Circuits Corporation |
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78 / 83 page  440GP – Power PC 440GP Embedded Processor 78 AMCC Revision 1.07 – October 4, 2007 Data Sheet Example 2: In this example Read Clock is delayed almost 1/2 cycle. Without ECC, Stage 2 data can be sampled at (2). If ECC is enabled, Stage 3 data must be sampled (see Example 3). In this example, TT = 1.5ns and TTE = 4.3ns at worst case conditions. DDR SDRAM Read Cycle Timing—Example 2 DQS at pin PLB Clock Read Clock Delayed TSIN Data at pin D0 D1 D2 D3 DQS Stage 1 C D0 D1 D2 D3 TDIN D0 D2 Data in Stage 1 D D1 D3 Data out Stage 1 High Low TP D0 D2 D1 D3 Data in at RDSP High Low without ECC TT = Propagation delay from Stage 2 input to RDSP input w/o ECC D0 D2 D1 D3 Data out Stage 2 High Low Data out at RDSP High Low (2) without ECC TP D0 D2 D1 D3 Data in at RDSP High Low with ECC D0 D2 D1 D3 TTE = Propagation delay from Stage 2 input to RDSP input with ECC TT TTE D0 D2 |
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