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PPC440GP-3CC466C Datasheet(PDF) 79 Page - Applied Micro Circuits Corporation |
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PPC440GP-3CC466C Datasheet(HTML) 79 Page - Applied Micro Circuits Corporation |
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79 / 83 page  440GP – Power PC 440GP Embedded Processor AMCC 79 Revision 1.07 – October 4, 2007 Data Sheet Example 3: In this example, ECC is enabled. This requires that Stage 3 data be sampled at (3). If ECC is disabled, the system will still work, but there will be more latency before the data is sampled into RDSP. Again, TT = 1.5ns and TTE = 4.3ns at worst case conditions. DDR SDRAM Read Cycle Timing—Example 3 DQS at pin PLB Clock Read Clock Delayed TSIN Data at pin D0 D1 D2 D3 DQS Stage 1 C D0 D1 D2 D3 TDIN D0 D2 Data in Stage 1 D D1 D3 Data out Stage 1 High Low TP D0 D2 D1 D3 Data out Stage 3 High Low with ECC TT = Propagation delay from Stage 2 input to RDSP input w/o ECC D0 D2 D1 D3 Data out Stage 2 High Low Data out RDSP High Low (3) with ECC TP D0 D2 D1 D3 Data in at RDSP High Low with ECC D0 D2 D1 D3 TTE = Propagation delay from Stage 2 input to RDSP input with ECC TTE D0 D2 |
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