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Encrypted, or plain text EDIF netlist

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Floating Point Pipelined Adder Unit

ver 2.50

Fully synthesizable, static synchronous

design with no internal tri-states

OVERVIEW

The DFPADD uses the pipelined mathemat-

ics algorithm to compute sum of two argu-

ments. The input numbers format is accord-

ing to IEEE-754 standard. DFPADD supports

single precision real number. Add operation

was pipelined up to 5 levels. Input data are

fed every clock cycle. The first result appears

after 5 clock periods latency and next results

are available each clock cycle. Full IEEE-

754 precision and accuracy were included.

DELIVERABLES

Source code:

VHDL Source Code or/and

VERILOG Source Code or/and

VHDL & VERILOG test bench environ-

ment

Active-HDL automatic simulation mac-

ros

APPLI C ATION

NCSim automatic simulation macros

ModelSim automatic simulation macros

Math coprocessors

Tests with reference responses

DSP algorithms

Technical documentation

Installation notes

Embedded arithmetic coprocessor

HDL core specification

Data processing & control

Datasheet

Synthesis scripts

Example application

KEY FEATURES

Technical support

IP Core implementation support

Full IEEE-754 compliance

3 months maintenance

Single precision real format support

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Delivery the IP Core updates, minor

and major versions changes

Simple interface

●

Delivery the documentation updates

No programming required

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Phone & email support

5 levels pipeline

LICENSING

Full accuracy and precision

Comprehensible and clearly defined licensing

methods without royalty fees make using of

IP Core easy and simply.

Results available at every clock

Overflow, underflow and invalid operation

flags

Single Design

license allows using IP Core in

single FPGA bitstream and ASIC implemen-

Fully configurable