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DSP56321 Datasheet(PDF) 35 Page - Freescale Semiconductor, Inc |
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DSP56321 Datasheet(HTML) 35 Page - Freescale Semiconductor, Inc |
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35 / 84 page  AC Electrical Characteristics DSP56321 Technical Data, Rev. 11 Freescale Semiconductor 2-15 323 HAS deassertion to data strobe assertion 4 0.0 — 0.0 — 0.0 — 0.0 — ns 324 Host data input setup time before write data strobe deassertion6 4.95 — 4.5 — 4.13 — 4.0 — ns 325 Host data input hold time after write data strobe deassertion6 1.65 — 1.5 — 1.38 — 1.23 — ns 326 Read data strobe assertion to output data active from high impedance 5 HACK assertion to output data active from high impedance 1.65 — 1.5 — 1.38 — 1.23 — ns 327 Read data strobe assertion to output data valid5 HACK assertion to output data valid — 14.78 — 13.45 — 12.32 — 10.2 ns 328 Read data strobe deassertion to output data high impedance5 HACK deassertion to output data high impedance — 4.95 — 4.5 — 4.13 4.0 — ns 329 Output data hold time after read data strobe deassertion5 Output data hold time after HACK deassertion 1.65 — 1.5 — 1.38 — 1.23 — ns 330 HCS assertion to read data strobe deassertion5 TC + 4.95 9.95 — 9.05 — 8.3 — 7.77 — ns 331 HCS assertion to write data strobe deassertion6 8— 8— 8— 8— ns 332 HCS assertion to output data valid — 17 — 16 — 15 — 14 ns 333 HCS hold time after data strobe deassertion 4 0.0 — 0.0 — 0.0 — 0.0 — ns 334 Address (HAD[0–7]) setup time before HAS deassertion (HMUX=1) 2.31 — 2.1 — 1.93 — 1.76 — ns 335 Address (HAD[0–7]) hold time after HAS deassertion (HMUX=1) 1.65 — 1.5 — 1.38 — 1.23 — ns 336 HA[8–10] (HMUX=1), HA[0–2] (HMUX=0), HR/W setup time before data strobe assertion 4 •Read •Write 0 2.31 — — 0 2.1 — — 0 1.93 — — 0 1.76 — — ns ns 337 HA[8–10] (HMUX=1), HA[0–2] (HMUX=0), HR/W hold time after data strobe deassertion4 1.65 — 1.5 — 1.38 — 1.23 — ns 338 Delay from read data strobe deassertion to host request assertion for “Last Data Register” read5, 7, 8 TC + 2.64 7.64 — 7.19 — 6.81 — 6.28 — ns 339 Delay from write data strobe deassertion to host request assertion for “Last Data Register” write6, 7, 8 1.5 × TC + 2.64 10.14 — 9.47 — 8.9 — 8.1 — ns 340 Delay from data strobe assertion to host request deassertion for “Last Data Register” read or write (HROD=0)4, 7, 8 — 12.14 — 11.04 — 10.12 — 9.0 ns 341 Delay from data strobe assertion to host request deassertion for “Last Data Register” read or write (HROD=1, open drain host request)4, 7, 8, 9 —300.0 —300.0 — 300.0 —300.0 ns Table 2-10. Host Interface Timings1,2,12 (Continued) No. Characteristic10 Expression 200 MHz 220 MHz 240 MHz 275 MHz Uni t Min Max Min Max Min Max Min Max |
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