DSP56321 datasheet(12/84 Pages) FREESCALE

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DSP56321 Technical Data, Rev. 11

1-6

Freescale Semiconductor

Signals/Connections

1.5 Interrupt and Mode Control

The interrupt and mode control signals select the chip operating mode as it comes out of hardware reset. After

RESET is deasserted, these inputs are hardware interrupt request lines.

Table 1-8.

Interrupt and Mode Control

Signal Name

Type

State During

Reset

Signal Description

MODA

IRQA

Input

Schmitt-trigger

Input

Mode Select A—MODA, MODB, MODC, and MODD select one of 16 initial

chip operating modes, latched into the Operating Mode Register when the

RESET signal is deasserted.

External Interrupt Request A—After reset, this input becomes a level-

sensitive or negative-edge-triggered, maskable interrupt request input during

normal instruction processing. If the processor is in the STOP or WAIT

standby state and IRQA is asserted, the processor exits the STOP or WAIT

state.

MODB

IRQB

Input

Schmitt-trigger

Input

Mode Select B—MODA, MODB, MODC, and MODD select one of 16 initial

chip operating modes, latched into the Operating Mode Register when the

RESET signal is deasserted.

External Interrupt Request B—After reset, this input becomes a level-

sensitive or negative-edge-triggered, maskable interrupt request input during

normal instruction processing. If the processor is in the WAIT standby state

and IRQB is asserted, the processor exits the WAIT state.

MODC

IRQC

Input

Schmitt-trigger

Input

Mode Select C—MODA, MODB, MODC, and MODD select one of 16 initial

chip operating modes, latched into the Operating Mode Register when the

RESET signal is deasserted.

External Interrupt Request C—After reset, this input becomes a level-

sensitive or negative-edge-triggered, maskable interrupt request input during

normal instruction processing. If the processor is in the WAIT standby state

and IRQC is asserted, the processor exits the WAIT state.

MODD

IRQD

Input

Schmitt-trigger

Input

Mode Select D—MODA, MODB, MODC, and MODD select one of 16 initial

chip operating modes, latched into the Operating Mode Register when the

RESET signal is deasserted.

External Interrupt Request D—After reset, this input becomes a level-

sensitive or negative-edge-triggered, maskable interrupt request input during

normal instruction processing. If the processor is in the WAIT standby state

and IRQD is asserted, the processor exits the WAIT state.

RESET

Input

Schmitt-trigger

Input

Reset—Places the chip in the Reset state and resets the internal phase

generator. The Schmitt-trigger input allows a slowly rising input (such as a

capacitor charging) to reset the chip reliably. When the RESET signal is

deasserted, the initial chip operating mode is latched from the MODA, MODB,

MODC, and MODD inputs. The RESET signal must be asserted after

powerup.

PINIT

NMI

Input

Schmitt-trigger

Input

PLL Initial—During assertion of RESET, the value of PINIT determines

whether the DPLL is enabled or disabled.

Nonmaskable Interrupt—After RESET deassertion and during normal

instruction processing, this Schmitt-trigger input is the negative-edge-triggered

NMI request.

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