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TMP86FS49AIUG Datasheet(PDF) 42 Page - Toshiba Semiconductor |
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TMP86FS49AIUG Datasheet(HTML) 42 Page - Toshiba Semiconductor |
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42 / 296 page ![]() Page 26 2. Operational Description 2.2 System Clock Controller TMP86FS49AIUG • Start the IDLE0 and SLEEP0 modes Stop (Disable) peripherals such as a timer counter. To start IDLE0 and SLEEP0 modes, set SYSCR2<TGHALT> to “1”. • Release the IDLE0 and SLEEP0 modes IDLE0 and SLEEP0 modes include a normal release mode and an interrupt release mode. These modes are selected by interrupt master flag (IMF), the individual interrupt enable flag of TBT and TBTCR<TBTEN>. After releasing IDLE0 and SLEEP0 modes, the SYSCR2<TGHALT> is automatically cleared to “0” and the operation mode is returned to the mode preceding IDLE0 and SLEEP0 modes. Before starting the IDLE0 or SLEEP0 mode, when the TBTCR<TBTEN> is set to “1”, INTTBT interrupt latch is set to “1”. IDLE0 and SLEEP0 modes can also be released by inputting low level on the RESET pin. After releasing reset, the operation mode is started from NORMAL1 mode. Note: IDLE0 and SLEEP0 modes start/release without reference to TBTCR<TBTEN> setting. (1) Normal release mode (IMF •EF7•TBTCR<TBTEN> = “0”) IDLE0 and SLEEP0 modes are released by the source clock falling edge, which is setting by the TBTCR<TBTCK>. After the falling edge is detected, the program operation is resumed from the instruction following the IDLE0 and SLEEP0 modes start instruction. Before starting the IDLE0 or SLEEP0 mode, when the TBTCR<TBTEN> is set to “1”, INTTBT interrupt latch is set to “1”. (2) Interrupt release mode (IMF •EF7•TBTCR<TBTEN> = “1”) IDLE0 and SLEEP0 modes are released by the source clock falling edge, which is setting by the TBTCR<TBTCK> and INTTBT interrupt processing is started. Note 1: Because returning from IDLE0, SLEEP0 to NORMAL1, SLOW1 is executed by the asynchro- nous internal clock, the period of IDLE0, SLEEP0 mode might be the shorter than the period set- ting by TBTCR<TBTCK>. Note 2: When a watchdog timer interrupt is generated immediately before IDLE0/SLEEP0 mode is started, the watchdog timer interrupt will be processed but IDLE0/SLEEP0 mode will not be started. |
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