LAN9252SLASHML datasheet(71/329 Pages) MICROCHIP

71 / 329 page

 2015 Microchip Technology Inc.

DS00001909A-page 71

LAN9252

16-BIT READS AND WRITES TO CONSTANT ADDRESS

The address is latched sequentially from AD[7:0]. AD[15:8] is not used or driven for the address phase. A mix of reads

and writes on AD[15:0] follows.

8-BIT READ

The address is latched sequentially from AD[7:0]. A read on AD[7:0] follows. AD[15:8] pins are not used or driven. The

cycle is repeated for the other BYTEs of the DWORD.

Note:

Generally, two 16-bit reads to opposite WORDs of the same DWORD are required, with at least the lower

address changing using ALELO. 16-bit reads and writes to the same WORD is a special case.

FIGURE 9-7:

MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 16-BIT READS

AND WRITES CONSTANT ADDRESS

FIGURE 9-8:

MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 8-BIT READS

ALELO

ALEHI

Address Low

Address High

Data 15:8

Data 7:0

Optional

AD[15:8]

AD[7:0]

Data 15:8

Data 7:0

Data 15:8

Data 7:0

Data 15:8

Data 7:0

Data 15:8

Data 7:0

AD[15:8]

ALELO

ALEHI

AD[7:0]

Address Low

Address High

Data 7:0

Optional

Address+1 Low Address High

Data 15:8

Optional

Address+2 Low Address High

Data 23:16

Address+3 Low Address High

Data 31:24

Hi-Z

Optional

LAN9252/ML Datasheet(PDF) 71 Page - Microchip Technology

LAN9252/ML Datasheet(HTML) 71 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL