8.2.3 Application Curve

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

0

10

20

30

40

50

60

70

80

90

100

Time (ns)

MCLK_IN

CLK_OUT1

V

= 3.3V

C

= 1µF

BATT

VLDO

C

= 0.1µF C

= 30pF

BATT

OUT

Figure 8-3. Sine Wave Input vs Output

8.3 Power Supply Recommendations

General power supply recommendations are to be considered for the CDC3RL02. These include:

• Decoupling capacitors placed close to the VBATT pin of typical values (1μF)

• VBATT be within the recommended voltage range

8.4 Layout

8.4.1 Layout Guidelines

To provide reliability of the device, following common printed-circuit board layout guidelines is recommended.

• Bypass capacitors must be used on power supplies and must be placed as close as possible to the VBATT pin

• Short trace-lengths must be used to avoid excessive loading

• For improved performance on the clock output lines, use a ground trace on the sides of the clock trace to

minimize crosstalk and EMI

8.4.2 Layout Example

A1

0402 Decoupling

Cap

VBATT

VLDO

MCLK_IN

GND

CLK_REQ2

CLK_REQ1

CLK_OUT2

CLK_OUT1

= Via to GND Plane

= GND Trace

Figure 8-4. Example Layout for YFP Package

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CDC3RL02

SCHS371H – NOVEMBER 2009 – REVISED OCTOBER 2024

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Product Folder Links: CDC3RL02