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L9679P Datasheet(PDF) 50 Page - STMicroelectronics |
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L9679P Datasheet(HTML) 50 Page - STMicroelectronics |
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50 / 279 page  Start-up and power control L9679P 50/279 DS11627 Rev 7 6.12 Reset control The device provides reset logic to safely control system operation in the event of internal ECU failures. Several internal reset signals are generated depending on the type of failure detected. In Figure 25 the voltage monitoring diagram is shown. Figure 25. Internal voltage monitors An active low pin output (RESET pin) is driven from the L9679P to allow resetting of external devices such as the microcontroller, sensors, and other ICs within the ECU. Three internal reset signals are generated by the device: POR Power On Reset - This reset is asserted when a failure is detected in the internal supplies or bandgap circuits. When active, all other resets are asserted. WSM_RESET Watchdog State Machine Reset - This reset is generated when the POR is active or when a failure is detected in the VCC supply. SSM_RESET System State Machine Reset - This reset is asserted when the POR or the WSM_RESET are active, or when a failure is detected in either Watchdog state machine. The RESET pin is the active-low signal driven on the output pin, and is an inverted form of SSM_RESET. The cause of the RESET activation is latched and reported into the Fault Status Register FLTSR and cleared upon SPI reading. During the RESET event the logic is under reset but the FLTSR is not reset. So the fault info will be available as soon as the IC will be out of reset. BSTGND GNDSUBx GNDD GNDA VDD VINT3V3 (Reference) VBGR Monitor BSTGND Monitor GNDD Monitor GNDA Monitor VCC Monitor CVDD Monitor VINT3V3 (Monitor) VBGM VCC_UV VCC_OV UV_CVDD OV_CVDD UV_VINT3V3 OV_VINT3V3 Controlling all supplies Reference for VBG_READY BSTGND_loss GND_ERR GNDD_ERR GNDA_ERR VCC_ERR VREG_ERR GADG1406180818PS |
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