STPM098C datasheet(66/110 Pages) STMICROELECTRONICS

66 / 110 page

If the current read on a phase differs from the average of all phases current readings by more than a threshold

value, then a dedicated error flag is raised.

(24)

ISENi−CFILTVREF1 −1m Σj=1mISENj−CFILTVREF1 ≥IOUTn_sharing_wr_th,theIOUTn_SHARING_WRflag

is set.

Where m is the number of active phases for the specific loop.

The reference thresholds for the IOUTn overbalance monitor unit IOUTn_sharing_wr_th can be separately

configured for loop 1 and 2 through a dedicated PMBus™ register as follows:

IOUTnSHARINGWRTH=IOUTMONUMBtℎlsb×IOUTnSHARINGWRTH5:0

Where:

IOUT_MON_UMB_th_lsb is the minimum voltage step [0.94 A].

IOUTn_SHARING_WR_TH [5:0] are the dedicated PMBus™ configuration bits.

The default value is IOUTn_SHARING_WR_TH = 0x03.

In case IOUTm_SHARING_WR_TH = 0x00, the related overcurrent monitor function is disabled and no detection

is performed.

The absolute value of the maximum input voltage slew rate detectable by IOUT monitor is given by

IOUT_adc_lsb/IOUT_adc_latency.

Figure 55. Phase current overbalance timing diagram

ISENn-CFILT/VREF1

IOUTn_SHARING_WR

(Internal signal)

UNBALANCE

IOUTn_SHARING_WR_TH

(ISENj−CFILT/VREF1)−1M

(ISENj−CFILT/VREF1)

Mj=1

1M (ISENj−CFILT/VREF1)

j=1

OPERATIVE

-IOUTn_SHARING_WR_TH

IOUTn_SHARING_WR_TH

UNBALANCE

T_iout_umb_detect_dly

STPM098C

Functional description

DS14440 - Rev 1

page 66/110

STPM098C Datasheet(PDF) 66 Page - STMicroelectronics